Hardware
/
VexRiscv
mirror of https://github.com/SpinalHDL/VexRiscv.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Bench DecoderPlugin

This commit is contained in:
Dolu1990 2021-05-10 10:47:09 +02:00
parent e78c0546a0
commit fe739b907a
4 changed files with 85 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

70
src/main/scala/vexriscv/demo/SynthesisBench.scala
View File

@ -6,6 +6,7 @@ import spinal.lib.eda.bench._
import spinal.lib.eda.icestorm.IcestormStdTargets
import spinal.lib.eda.xilinx.VivadoFlow
import spinal.lib.io.InOutWrapper
import vexriscv.demo.smp.VexRiscvSmpClusterGen
import vexriscv.plugin.CsrAccess.{READ_ONLY, READ_WRITE, WRITE_ONLY}
import vexriscv.{VexRiscv, VexRiscvConfig, plugin}
import vexriscv.plugin.{BranchPlugin, CsrPlugin, CsrPluginConfig, DBusSimplePlugin, DecoderSimplePlugin, FullBarrelShifterPlugin, HazardSimplePlugin, IBusSimplePlugin, IntAluPlugin, LightShifterPlugin, NONE, RegFilePlugin, SrcPlugin, YamlPlugin}
@ -200,9 +201,78 @@ object VexRiscvSynthesisBench {
SpinalConfig(inlineRom = true).generateVerilog(wrap(new VexRiscv(LinuxGen.configFull(false, true, withSmp = true))).setDefinitionName(getRtlPath().split("\\.").head))
}
val linuxFpuSmp = new Rtl {
override def getName(): String = "VexRiscv linux Fpu SMP"
override def getRtlPath(): String = "VexRiscvLinuxFpuSmp.v"
SpinalConfig(inlineRom = true).generateVerilog(wrap(new VexRiscv(
VexRiscvSmpClusterGen.vexRiscvConfig(
hartId = 0,
ioRange = _ (31 downto 28) === 0xF,
resetVector = 0x80000000l,
iBusWidth = 64,
dBusWidth = 64,
loadStoreWidth = 64,
iCacheSize = 4096*2,
dCacheSize = 4096*2,
iCacheWays = 2,
dCacheWays = 2,
withFloat = true,
withDouble = true,
externalFpu = false,
simHalt = true
))).setDefinitionName(getRtlPath().split("\\.").head))
}
val linuxFpuSmpNoDecoder = new Rtl {
override def getName(): String = "VexRiscv linux Fpu SMP without decoder"
override def getRtlPath(): String = "VexRiscvLinuxFpuSmpNoDecoder.v"
SpinalConfig(inlineRom = true).generateVerilog(wrap(new VexRiscv(
VexRiscvSmpClusterGen.vexRiscvConfig(
hartId = 0,
ioRange = _ (31 downto 28) === 0xF,
resetVector = 0x80000000l,
iBusWidth = 64,
dBusWidth = 64,
loadStoreWidth = 64,
iCacheSize = 4096*2,
dCacheSize = 4096*2,
iCacheWays = 2,
dCacheWays = 2,
withFloat = true,
withDouble = true,
externalFpu = false,
simHalt = true,
decoderIsolationBench = true
))).setDefinitionName(getRtlPath().split("\\.").head))
}
val linuxFpuSmpStupidDecoder = new Rtl {
override def getName(): String = "VexRiscv linux Fpu SMP stupid decoder"
override def getRtlPath(): String = "VexRiscvLinuxFpuSmpStupidDecoder.v"
SpinalConfig(inlineRom = true).generateVerilog(wrap(new VexRiscv(
VexRiscvSmpClusterGen.vexRiscvConfig(
hartId = 0,
ioRange = _ (31 downto 28) === 0xF,
resetVector = 0x80000000l,
iBusWidth = 64,
dBusWidth = 64,
loadStoreWidth = 64,
iCacheSize = 4096*2,
dCacheSize = 4096*2,
iCacheWays = 2,
dCacheWays = 2,
withFloat = true,
withDouble = true,
externalFpu = false,
simHalt = true,
decoderStupid = true
))).setDefinitionName(getRtlPath().split("\\.").head))
}
val rtls = List(
// linuxFpuSmp, linuxFpuSmpNoDecoder, linuxFpuSmpStupidDecoder
twoStage, twoStageBarell, twoStageMulDiv, twoStageAll,
threeStage, threeStageBarell, threeStageMulDiv, threeStageAll,
smallestNoCsr, smallest, smallAndProductive, smallAndProductiveWithICache, fullNoMmuNoCache, noCacheNoMmuMaxPerf, fullNoMmuMaxPerf, fullNoMmu, full, linuxBalanced, linuxBalancedSmp

6
src/main/scala/vexriscv/demo/smp/VexRiscvSmpCluster.scala
View File

@ -181,6 +181,8 @@ object VexRiscvSmpClusterGen {
withDouble : Boolean = false,
externalFpu : Boolean = true,
simHalt : Boolean = false,
decoderIsolationBench : Boolean = false,
decoderStupid : Boolean = false,
regfileRead : RegFileReadKind = plugin.ASYNC,
rvc : Boolean = false
) = {
@ -254,7 +256,9 @@ object VexRiscvSmpClusterGen {
)
),
new DecoderSimplePlugin(
catchIllegalInstruction = true
catchIllegalInstruction = true,
decoderIsolationBench = decoderIsolationBench,
stupidDecoder = decoderStupid
),
new RegFilePlugin(
regFileReadyKind = regfileRead,

11
src/main/scala/vexriscv/plugin/DecoderSimplePlugin.scala
View File

@ -47,7 +47,9 @@ case class Masked(value : BigInt,care : BigInt){
class DecoderSimplePlugin(catchIllegalInstruction : Boolean = false,
throwIllegalInstruction : Boolean = false,
assertIllegalInstruction : Boolean = false,
forceLegalInstructionComputation : Boolean = false) extends Plugin[VexRiscv] with DecoderService {
forceLegalInstructionComputation : Boolean = false,
decoderIsolationBench : Boolean = false,
stupidDecoder : Boolean = false) extends Plugin[VexRiscv] with DecoderService {
override def add(encoding: Seq[(MaskedLiteral, Seq[(Stageable[_ <: BaseType], Any)])]): Unit = encoding.foreach(e => this.add(e._1,e._2))
override def add(key: MaskedLiteral, values: Seq[(Stageable[_ <: BaseType], Any)]): Unit = {
val instructionModel = encodings.getOrElseUpdate(key,ArrayBuffer[(Stageable[_ <: BaseType], BaseType)]())
@ -91,7 +93,7 @@ class DecoderSimplePlugin(catchIllegalInstruction : Boolean = false,
val stageables = (encodings.flatMap(_._2.map(_._1)) ++ defaults.map(_._1)).toList.distinct
val stupidDecoder = false
if(stupidDecoder){
if (detectLegalInstructions) insert(LEGAL_INSTRUCTION) := False
for(stageable <- stageables){
@ -162,6 +164,11 @@ class DecoderSimplePlugin(catchIllegalInstruction : Boolean = false,
insert(ASSERT_ERROR) := arbitration.isValid || reg
}
if(decoderIsolationBench){
KeepAttribute(RegNext(KeepAttribute(RegNext(decodedBits.removeAssignments().asInput()))))
out(Bits(32 bits)).setName("instruction") := KeepAttribute(RegNext(KeepAttribute(RegNext(input(INSTRUCTION)))))
}
//Unpack decodedBits and insert fields in the pipeline
offset = 0
stageables.foreach(e => {

2
src/main/scala/vexriscv/plugin/FpuPlugin.scala
View File

@ -83,7 +83,7 @@ class FpuPlugin(externalFpu : Boolean = false,
)
def arg(v : Int) = FPU_ARG -> U(v, 2 bits)
def arg(v : Int) = FPU_ARG -> B(v, 2 bits)
val decoderService = pipeline.service(classOf[DecoderService])
decoderService.addDefault(FPU_ENABLE, False)