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Fix LrSc for configs without mmu

This commit is contained in:
Dolu1990 2020-04-04 22:54:35 +02:00
parent c9bbf0d12a
commit ff074459ad
1 changed files with 1 additions and 1 deletions
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2
src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala
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@ -469,7 +469,7 @@ class DBusSimplePlugin(catchAddressMisaligned : Boolean = false,
val atomic = withLrSc generate new Area{ val atomic = withLrSc generate new Area{
val reserved = RegInit(False) val reserved = RegInit(False)
insert(ATOMIC_HIT) := reserved insert(ATOMIC_HIT) := reserved
when(arbitration.isFiring && input(MEMORY_ENABLE) && input(MEMORY_ATOMIC) && !input(MMU_FAULT) && !skipCmd){ when(arbitration.isFiring && input(MEMORY_ENABLE) && input(MEMORY_ATOMIC) && (if(mmuBus != null) !input(MMU_FAULT) else True) && !skipCmd){
reserved := !input(MEMORY_STORE) reserved := !input(MEMORY_STORE)
} }
when(input(MEMORY_STORE) && input(MEMORY_ATOMIC) && !input(ATOMIC_HIT)){ when(input(MEMORY_STORE) && input(MEMORY_ATOMIC) && !input(ATOMIC_HIT)){