Hardware/VexRiscv
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VexRiscv/src
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Dolu1990 a6c29766da CsrPlugin now force privilegeGen when withPrivilegedDebug is enabled
2022-10-26 15:48:34 +02:00
..
main CsrPlugin now force privilegeGen when withPrivilegedDebug is enabled 2022-10-26 15:48:34 +02:00
test Add official RISC-V debug support (WIP, but can already load / step / run code via openocd telnet) 2022-10-19 12:36:45 +02:00