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VexRiscv
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https://github.com/SpinalHDL/VexRiscv.git
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3b3bbd48b9
VexRiscv
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Murax
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iCE40-hx8k_breakout_board
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Dolu1990
3b3bbd48b9
SpinalHDL 1.1.3 => Now Verilog rom are emited into separated bin files
2018-01-20 18:29:33 +01:00
..
makefile
SpinalHDL 1.1.3 => Now Verilog rom are emited into separated bin files
2018-01-20 18:29:33 +01:00
toplevel.pcf
Clean script folder
2017-12-29 13:18:14 +01:00
toplevel.v
Clean script folder
2017-12-29 13:18:14 +01:00