270 lines
10 KiB
Markdown
270 lines
10 KiB
Markdown
## Index
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- [Description](#description)
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- [Area usage and maximal frequency](#area-usage-and-maximal-frequency)
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- [Dependencies](#dependencies)
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- [CPU generation](#cpu-generation)
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- [Regression tests](#regression-tests)
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- [Interactive debug of the simulated CPU via GDB OpenOCD and Verilator](#interactive-debug-of-the-simulated-cpu-via-gdb-openocd-and-verilator)
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- [Using eclipse to run the software and debug it](#using-eclipse-to-run-the-software-and-debug-it)
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- [Briey SoC](#briey-soc)
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- [Build the RISC-V GCC](#build-the-risc-v-gcc)
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- [Cpu plugin structure](#cpu-plugin-structure)
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## Description
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This repository host an RISC-V implementation written in SpinalHDL. There is some specs :
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- RV32IM instruction set
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- Interrupts and exception handling with the Machine mode from the riscv-privileged-v1.9.1 specification.
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- Pipelined on 5 stages (Fetch, Decode, Execute, Memory, WriteBack)
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- 1.16 DMIPS/Mhz when all features are enabled extension
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- Optimized for FPGA
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- Optional MUL/DIV/REM extension
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- Optional instruction and data caches
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- Optional MMU
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- Two implementation of shift instructions, Single cycle / shiftNumber cycle
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- Each stage could have bypass or interlock hazard logic
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- FreeRTOS port https://github.com/Dolu1990/FreeRTOS-RISCV
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The hardware description of this CPU is done by using an very software oriented approach
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(without any overhead in the generated hardware). There is a list of software concepts used :
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- There is very few fixed things. Nearly everything is plugin based. The PC manager is a plugin, the register file is a plugin, the hazard controller is a plugin ...
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- There is an automatic a tool which allow plugins to insert data in the pipeline at a given stage, and allow other plugins to read it in another stages through automatic pipelining.
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- There is an service system which provide a very dynamic framework. As instance, a plugin could provide an exception service which could then be used by others plugins to emit exceptions from the pipeline.
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## Area usage and maximal frequency
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The following number where obtains by synthesis the CPU as toplevel without any specific synthesis option to save area or to get better maximal frequency (neutral).
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The used CPU corresponding configuration can be find in src/scala/VexRiscv/demo.
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```
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VexRiscv smallest (RV32I, 0.47 DMIPS/Mhz, no datapath bypass, no interrupt) ->
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Artix 7 -> 324 Mhz 478 LUT 539 FF
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Cyclone V -> 187 Mhz 341 ALMs
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Cyclone IV -> 180 Mhz 736 LUT 529 FF
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Cyclone II -> 156 Mhz 740 LUT 528 FF
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VexRiscv smallest (RV32I, 0.47 DMIPS/Mhz, no datapath bypass) ->
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Artix 7 -> 335 Mhz 560 LUT 589 FF
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Cyclone V -> 182 Mhz 420 ALMs
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Cyclone IV -> 160 Mhz 852 LUT 579 FF
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Cyclone II -> 144 Mhz 844 LUT 578 FF
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VexRiscv full (RV32IM, 1.14 DMIPS/Mhz, I$, D$, single cycle barrel shifter, debug module, catch exceptions, static branch) ->
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Artix 7 -> 249 Mhz 1862 LUT 1498 FF
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Cyclone V -> 133 Mhz 1272 ALMs
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Cyclone IV -> 116 Mhz 2727 LUT 1759 FF
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Cyclone II -> 105 Mhz 2771 LUT 1758 FF
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VexRiscv full with MMU (RV32IM, 1.16 DMIPS/Mhz, I$, D$, single cycle barrel shifter, debug module, catch exceptions, static branch, MMU) ->
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Artix 7 -> 210 Mhz 2104 LUT 2017 FF
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Cyclone V -> 115 Mhz 1503 ALMs
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Cyclone IV -> 100 Mhz 3145 LUT 2278 FF
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Cyclone II -> 92 Mhz 3195 LUT 2279 FF
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```
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## Dependencies
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On Ubuntu 14 :
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```sh
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# JAVA JDK 7 or 8
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sudo apt-get install openjdk-7-jdk
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# SBT
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echo "deb https://dl.bintray.com/sbt/debian /" | sudo tee -a /etc/apt/sources.list.d/sbt.list
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sudo apt-key adv --keyserver hkp://keyserver.ubuntu.com:80 --recv 2EE0EA64E40A89B84B2DF73499E82A75642AC823
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sudo apt-get update
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sudo apt-get install sbt
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# Verilator (for sim only)
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sudo apt-get install git make autoconf g++ flex bison
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git clone http://git.veripool.org/git/verilator # Only first time
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unsetenv VERILATOR_ROOT # For csh; ignore error if on bash
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unset VERILATOR_ROOT # For bash
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cd verilator
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git pull # Make sure we're up-to-date
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git tag # See what versions exist
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autoconf # Create ./configure script
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./configure
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make
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sudo make install
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```
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## CPU generation
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You can find two example of CPU instantiation in :
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- src/main/scala/VexRiscv/GenFull.scala
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- src/main/scala/VexRiscv/GenSmallest.scala
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To generate the corresponding RTL as a VexRiscv.v file, run (it could take time the first time you run it):
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NOTE :
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The VexRiscv could need the unreleased master-head of SpinalHDL. If it fail to compile, just get the SpinalHDL repository and do a "sbt publish-local" in it.
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```sh
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sbt "run-main VexRiscv.demo.GenFull"
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# or
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sbt "run-main VexRiscv.demo.GenSmallest"
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```
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## Regression tests
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To run tests (need the verilator simulator), go in the src/test/cpp/regression folder and run :
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```sh
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# To test the GenFull CPU
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make clean run
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# To test the GenSmallest CPU
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make clean run IBUS=IBUS_SIMPLE DBUS=DBUS_SIMPLE CSR=no MMU=no DEBUG_PLUGIN=no MUL=no DIV=no
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```
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## Interactive debug of the simulated CPU via GDB OpenOCD and Verilator
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It's as described to run tests, but you just have to add DEBUG_PLUGIN_EXTERNAL=yes in the make arguments.
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Work for the GenFull, but not for the GenSmallest as this configuration has no debug module.
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Then you can use the https://github.com/SpinalHDL/openocd_riscv tool to create a GDB server connected to the target (the simulated CPU)
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```sh
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#in the VexRiscv repository, to run the simulation on which one OpenOCD can connect itself =>
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sbt "run-main VexRiscv.demo.GenFull"
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cd src/test/cpp/regression
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make run DEBUG_PLUGIN_EXTERNAL=yes
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#In the openocd git, after building it =>
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src/openocd -c "set VEXRISCV_YAML PATH_TO_THE_GENERATED_CPU0_YAML_FILE" -f tcl/target/vexriscv_sim.cfg
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#Run a GDB session with an elf RISCV executable (GenFull CPU)
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YourRiscvToolsPath/bin/riscv32-unknown-elf-gdb VexRiscvRepo/src/test/resources/elf/uart.elf
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target remote localhost:3333
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monitor reset halt
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load
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continue
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# Now it should print messages in the Verilator simulation of the CPU
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```
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## Using eclipse to run the software and debug it
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You can use the eclipse + zilin embedded CDT plugin to do it (http://opensource.zylin.com/embeddedcdt.html). Tested with Helios Service Release 2 and the corresponding zylin plugin.
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## Briey SoC
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As a demonstrator, a SoC named Briey is implemented in src/main/scala/VexRiscv/demo/Briey.scala. This SoC is very similar to the Pinsec one :
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<img src="http://cdn.rawgit.com/SpinalHDL/SpinalDoc/dd17971aa549ccb99168afd55aad274bbdff1e88/asset/picture/pinsec_hardware.svg" align="middle" width="300">
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To generate the Briey SoC Hardware :
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```sh
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sbt "run-main VexRiscv.demo.Briey"
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```
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To run the verilator simulation of the Briey SoC which can be then connected to OpenOCD/GDB, first get those dependencies :
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```sh
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sudo apt-get install build-essential xorg-dev libudev-dev libts-dev libgl1-mesa-dev libglu1-mesa-dev libasound2-dev libpulse-dev libopenal-dev libogg-dev libvorbis-dev libaudiofile-dev libpng12-dev libfreetype6-dev libusb-dev libdbus-1-dev zlib1g-dev libdirectfb-dev libsdl2-dev
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```
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Then go in src/test/cpp/briey and run the simulation with (UART TX is printed in the terminal, VGA is displayed in a GUI):
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```sh
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make clean run
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```
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To connect OpenOCD (https://github.com/SpinalHDL/openocd_riscv) to the simulation :
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```sh
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src/openocd -f tcl/interface/jtag_tcp.cfg -c "set BRIEY_CPU0_YAML /home/spinalvm/Spinal/VexRiscv/cpu0.yaml" -f tcl/target/briey.cfg
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```
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You can find multiples software examples and demo there : https://github.com/SpinalHDL/BrieySoftware
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You can find some FPGA project which instantiate the Briey SoC there (DE1-SoC, DE0-Nano): https://drive.google.com/drive/folders/0B-CqLXDTaMbKZGdJZlZ5THAxRTQ?usp=sharing
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## Build the RISC-V GCC
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To install in /opt/ the rv32i and rv32im gcc, do the following (will take hours):
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```sh
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# Be carefull, sometime the git clone has issue to successfully clone riscv-gnu-toolchain.
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sudo apt-get install autoconf automake autotools-dev curl libmpc-dev libmpfr-dev libgmp-dev gawk build-essential bison flex texinfo gperf libtool patchutils bc zlib1g-dev -y
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git clone --recursive https://github.com/riscv/riscv-gnu-toolchain riscv-gnu-toolchain
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cd riscv-gnu-toolchain
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echo "Starting RISC-V Toolchain build process"
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ARCH=rv32im
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rmdir -rf $ARCH
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mkdir $ARCH; cd $ARCH
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../configure --prefix=/opt/$ARCH --with-arch=$ARCH --with-abi=ilp32
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sudo make -j4
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cd ..
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ARCH=rv32i
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rmdir -rf $ARCH
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mkdir $ARCH; cd $ARCH
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../configure --prefix=/opt/$ARCH --with-arch=$ARCH --with-abi=ilp32
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sudo make -j4
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cd ..
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echo -e "\\nRISC-V Toolchain installation completed!"
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```
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## Cpu plugin structure
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There is an example of an pseudo ALU plugin :
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```scala
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//Define an signal name/type which could be used in the pipeline
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object ALU_ENABLE extends Stageable(Bool)
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object ALU_OP extends Stageable(Bits(2 bits)) // ADD, SUB, AND, OR
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object ALU_SRC1 extends Stageable(UInt(32 bits))
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object ALU_SRC2 extends Stageable(UInt(32 bits))
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object ALU_RESULT extends Stageable(UInt(32 bits))
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class AluPlugin() extends Plugin[VexRiscv]{
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//Callback to setup the plugin and ask for different services
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override def setup(pipeline: VexRiscv): Unit = {
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import pipeline.config._
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//Do some setups as for example specifying some instruction decoding by using the Decoding service
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val decoderService = pipeline.service(classOf[DecoderService])
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decoderService.addDefault(ALU_ENABLE,False)
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decodingService.add(List(
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M"0100----------" -> List(ALU_ENABLE -> True, ALU_OP -> B"01"),
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M"0110---11-----" -> List(ALU_ENABLE -> True, ...)
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))
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}
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//Callback to build the hardware logic
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override def build(pipeline: VexRiscv): Unit = {
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import pipeline._
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execute plug new Area {
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import execute._
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//Add some logic in the execute stage
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insert(ALU_RESULT) := input(ALU_OP).mux(
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B"00" -> input(ALU_SRC1) + input(ALU_SRC2),
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B"01" -> input(ALU_SRC1) - input(ALU_SRC2),
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B"10" -> input(ALU_SRC1) & input(ALU_SRC2),
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B"11" -> input(ALU_SRC1) | input(ALU_SRC2),
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)
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}
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writeBack plug new Area {
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import writeBack._
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//Add some logic in the execute stage
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when(input(ALU_ENABLE)){
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input(REGFILE_WRITE_DATA) := input(ALU_RESULT)
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}
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}
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}
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}
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```
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