533 lines
20 KiB
Markdown
533 lines
20 KiB
Markdown
## Index
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- [Description](#description)
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- [Area usage and maximal frequency](#area-usage-and-maximal-frequency)
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- [Dependencies](#dependencies)
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- [CPU generation](#cpu-generation)
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- [Regression tests](#regression-tests)
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- [Interactive debug of the simulated CPU via GDB OpenOCD and Verilator](#interactive-debug-of-the-simulated-cpu-via-gdb-openocd-and-verilator)
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- [Using eclipse to run the software and debug it](#using-eclipse-to-run-the-software-and-debug-it)
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- [Briey SoC](#briey-soc)
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- [Murax SoC](#murax-soc)
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- [Build the RISC-V GCC](#build-the-risc-v-gcc)
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- [CPU parametrization and instantiation example](#cpu-parametrization-and-instantiation-example)
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- [Add a custom instruction to the CPU via the plugin system](#add-a-custom-instruction-to-the-cpu-via-the-plugin-system)
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- [CPU clock and resets](#cpu-clock-and-resets)
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## Description
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This repository host an RISC-V implementation written in SpinalHDL. There is some specs :
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- RV32IM instruction set
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- Pipelined on 5 stages (Fetch, Decode, Execute, Memory, WriteBack)
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- 1.16 DMIPS/Mhz when all features are enabled
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- Optimized for FPGA
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- AXI4 and Avalon ready
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- Optional MUL/DIV extension
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- Optional instruction and data caches
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- Optional MMU
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- Optional debug extension allowing eclipse debugging via an GDB >> openOCD >> JTAG connection
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- Optional interrupts and exception handling with the Machine and the User mode from the riscv-privileged-v1.9.1 spec.
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- Two implementation of shift instructions, Single cycle / shiftNumber cycles
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- Each stage could have bypass or interlock hazard logic
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- FreeRTOS port https://github.com/Dolu1990/FreeRTOS-RISCV
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The hardware description of this CPU is done by using an very software oriented approach
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(without any overhead in the generated hardware). There is a list of software concepts used :
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- There is very few fixed things. Nearly everything is plugin based. The PC manager is a plugin, the register file is a plugin, the hazard controller is a plugin ...
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- There is an automatic a tool which allow plugins to insert data in the pipeline at a given stage, and allow other plugins to read it in another stages through automatic pipelining.
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- There is an service system which provide a very dynamic framework. As instance, a plugin could provide an exception service which could then be used by others plugins to emit exceptions from the pipeline.
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## Area usage and maximal frequency
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The following number where obtains by synthesis the CPU as toplevel without any specific synthesis option to save area or to get better maximal frequency (neutral).<br>
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The clock constraint is set to a unattainable value, which tends to increase the design area.<br>
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The used CPU corresponding configuration can be find in src/scala/vexriscv/demo.
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```
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VexRiscv smallest (RV32I, 0.47 DMIPS/Mhz, no datapath bypass, no interrupt) ->
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Artix 7 -> 372 Mhz 568 LUT 603 FF
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Cyclone V -> 201 Mhz 347 ALMs
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Cyclone IV -> 190 Mhz 673 LUT 529 FF
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Cyclone II -> 154 Mhz 673 LUT 528 FF
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VexRiscv smallest (RV32I, 0.47 DMIPS/Mhz, no datapath bypass) ->
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Artix 7 -> 340 Mhz 562 LUT 589 FF
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Cyclone V -> 202 Mhz 387 ALMs
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Cyclone IV -> 180 Mhz 780 LUT 579 FF
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Cyclone II -> 149 Mhz 780 LUT 578 FF
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VexRiscv small and productive (RV32I, 0.78 DMIPS/Mhz) ->
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Artix 7 -> 309 Mhz 703 LUT 557 FF
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Cyclone V -> 152 Mhz 502 ALMs
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Cyclone IV -> 147 Mhz 1,062 LUT 552 FF
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Cyclone II -> 120 Mhz 1,072 LUT 551 FF
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VexRiscv full no cache (RV32IM, 1.14 DMIPS/Mhz, single cycle barrel shifter, debug module, catch exceptions, static branch) ->
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Artix 7 -> 310 Mhz 1391 LUT 934 FF
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Cyclone V -> 143 Mhz 935 ALMs
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Cyclone IV -> 123 Mhz 1,916 LUT 960 FF
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Cyclone II -> 108 Mhz 1,939 LUT 959 FF
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VexRiscv full (RV32IM, 1.14 DMIPS/Mhz, I$, D$, single cycle barrel shifter, debug module, catch exceptions, static branch) ->
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Artix 7 -> 250 Mhz 1911 LUT 1501 FF
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Cyclone V -> 132 Mhz 1,266 ALMs
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Cyclone IV -> 127 Mhz 2,733 LUT 1,762 FF
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Cyclone II -> 103 Mhz 2,791 LUT 1,760 FF
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VexRiscv full with MMU (RV32IM, 1.16 DMIPS/Mhz, I$, D$, single cycle barrel shifter, debug module, catch exceptions, dynamic branch, MMU) ->
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Artix 7 -> 223 Mhz 2085 LUT 2020 FF
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Cyclone V -> 110 Mhz 1,503 ALMs
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Cyclone IV -> 108 Mhz 3,153 LUT 2,281 FF
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Cyclone II -> 94 Mhz 3,187 LUT 2,281 FF
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```
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## Dependencies
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On Ubuntu 14 :
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```sh
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# JAVA JDK 7 or 8
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sudo apt-get install openjdk-8-jdk
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# SBT
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echo "deb https://dl.bintray.com/sbt/debian /" | sudo tee -a /etc/apt/sources.list.d/sbt.list
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sudo apt-key adv --keyserver hkp://keyserver.ubuntu.com:80 --recv 2EE0EA64E40A89B84B2DF73499E82A75642AC823
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sudo apt-get update
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sudo apt-get install sbt
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# Verilator (for sim only, realy need 3.9+, in general apt-get will give you 3.8)
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sudo apt-get install git make autoconf g++ flex bison
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git clone http://git.veripool.org/git/verilator # Only first time
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unsetenv VERILATOR_ROOT # For csh; ignore error if on bash
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unset VERILATOR_ROOT # For bash
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cd verilator
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git pull # Make sure we're up-to-date
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git tag # See what versions exist
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autoconf # Create ./configure script
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./configure
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make
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sudo make install
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```
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The VexRiscv need the unreleased master-head of SpinalHDL :
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```sh
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# Compile and localy publish the latest SpinalHDL
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rm -rf SpinalHDL
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git clone https://github.com/SpinalHDL/SpinalHDL.git
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cd SpinalHDL
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sbt clean compile publish-local
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cd ..
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```
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## CPU generation
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You can find two example of CPU instantiation in :
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- src/main/scala/vexriscv/GenFull.scala
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- src/main/scala/vexriscv/GenSmallest.scala
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To generate the corresponding RTL as a VexRiscv.v file, run (it could take time the first time you run it):
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NOTE :
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The VexRiscv could need the unreleased master-head of SpinalHDL. If it fail to compile, just get the SpinalHDL repository and do a "sbt clean compile publish-local" in it as described in the dependencies chapter.
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```sh
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sbt "run-main vexriscv.demo.GenFull"
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# or
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sbt "run-main vexriscv.demo.GenSmallest"
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```
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## Regression tests
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To run tests (need the verilator simulator), go in the src/test/cpp/regression folder and run :
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```sh
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# To test the GenFull CPU
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# (Don't worry about the CSR test not passing, basicaly the GenFull isn't the truly full version of the CPU, some CSR feature are disable in it)
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make clean run
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# To test the GenSmallest CPU
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make clean run IBUS=SIMPLE DBUS=SIMPLE CSR=no MMU=no DEBUG_PLUGIN=no MUL=no DIV=no
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```
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Those self tested tests include :
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- ISA tests from https://github.com/riscv/riscv-tests/tree/master/isa
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- Dhrystone benchmark
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- 24 tests FreeRTOS tests
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- Some handwritten tests to check the CSR, debug module and MMU plugins
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You can enable FreeRTOS tests by adding 'FREERTOS=yes' in the command line, will take time. Also, it use THREAD_COUNT host CPU threads to run multiple regression in parallel.
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## Interactive debug of the simulated CPU via GDB OpenOCD and Verilator
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It's as described to run tests, but you just have to add DEBUG_PLUGIN_EXTERNAL=yes in the make arguments.
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Work for the GenFull, but not for the GenSmallest as this configuration has no debug module.
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Then you can use the https://github.com/SpinalHDL/openocd_riscv tool to create a GDB server connected to the target (the simulated CPU)
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```sh
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#in the VexRiscv repository, to run the simulation on which one OpenOCD can connect itself =>
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sbt "run-main vexriscv.demo.GenFull"
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cd src/test/cpp/regression
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make run DEBUG_PLUGIN_EXTERNAL=yes
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#In the openocd git, after building it =>
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src/openocd -c "set VEXRISCV_YAML PATH_TO_THE_GENERATED_CPU0_YAML_FILE" -f tcl/target/vexriscv_sim.cfg
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#Run a GDB session with an elf RISCV executable (GenFull CPU)
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YourRiscvToolsPath/bin/riscv32-unknown-elf-gdb VexRiscvRepo/src/test/resources/elf/uart.elf
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target remote localhost:3333
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monitor reset halt
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load
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continue
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# Now it should print messages in the Verilator simulation of the CPU
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```
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## Using eclipse to run the software and debug it
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You can use the eclipse + zilin embedded CDT plugin to do it (http://opensource.zylin.com/embeddedcdt.html). Tested with Helios Service Release 2 (http://www.eclipse.org/downloads/download.php?file=/technology/epp/downloads/release/helios/SR2/eclipse-cpp-helios-SR2-linux-gtk-x86_64.tar.gz) and the corresponding zylin plugin.
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## Briey SoC
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As a demonstrator, a SoC named Briey is implemented in src/main/scala/vexriscv/demo/Briey.scala. This SoC is very similar to the Pinsec one :
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To generate the Briey SoC Hardware :
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```sh
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sbt "run-main vexriscv.demo.Briey"
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```
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To run the verilator simulation of the Briey SoC which can be then connected to OpenOCD/GDB, first get those dependencies :
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```sh
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sudo apt-get install build-essential xorg-dev libudev-dev libts-dev libgl1-mesa-dev libglu1-mesa-dev libasound2-dev libpulse-dev libopenal-dev libogg-dev libvorbis-dev libaudiofile-dev libpng12-dev libfreetype6-dev libusb-dev libdbus-1-dev zlib1g-dev libdirectfb-dev libsdl2-dev
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```
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Then go in src/test/cpp/briey and run the simulation with (UART TX is printed in the terminal, VGA is displayed in a GUI):
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```sh
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make clean run
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```
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To connect OpenOCD (https://github.com/SpinalHDL/openocd_riscv) to the simulation :
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```sh
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src/openocd -f tcl/interface/jtag_tcp.cfg -c "set BRIEY_CPU0_YAML /home/spinalvm/Spinal/VexRiscv/cpu0.yaml" -f tcl/target/briey.cfg
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```
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You can find multiples software examples and demo there : https://github.com/SpinalHDL/VexRiscvSocSoftware/tree/master/projects/briey
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You can find some FPGA project which instantiate the Briey SoC there (DE1-SoC, DE0-Nano): https://drive.google.com/drive/folders/0B-CqLXDTaMbKZGdJZlZ5THAxRTQ?usp=sharing
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There is some measurements of Briey SoC timings and area :
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```
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Artix 7 -> 256 Mhz 3302 LUT 3524 FF
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Cyclone V -> 126 Mhz 2,295 ALMs
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Cyclone IV -> 121 Mhz 4,781 LUT 3,713 FF
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Cyclone II -> 104 Mhz 4,902 LUT 3,718 FF
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```
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## Murax SoC
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Murax is a very light SoC (fit in ICE40 FPGA) which could work without any external component.
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- VexRiscv RV32I[M]
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- JTAG debugger (eclipse/GDB/openocd ready)
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- 8 kB of on-chip ram
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- Interrupt support
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- APB bus for peripherals
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- 32 GPIO pin
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- one 16 bits prescaler, two 16 bits timers
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- one UART with tx/rx fifo
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Depending the CPU configuration, on the ICE40-hx8k FPGA with icestorm for synthesis, the full SoC will get following area/performance :
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- RV32I interlocked stages => 51 Mhz, 2387 LC 0.37 DMIPS/Mhz
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- RV32I bypassed stages => 45 Mhz, 2718 LC 0.55 DMIPS/Mhz
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You can find its implementation there : src/main/scala/vexriscv/demo/Murax.scala
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To generate the Murax SoC Hardware :
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```sh
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# To generate the SoC without any content in the ram
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sbt "run-main vexriscv.demo.Murax"
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# To generate the SoC with a demo program in the SoC
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# Will blink led and echo UART RX to UART TX (in the verilator sim, type some text and press enter to send UART frames to the Murax RX pin)
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sbt "run-main vexriscv.demo.MuraxWithRamInit"
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```
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Then go in src/test/cpp/murax and run the simulation with :
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```sh
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make clean run
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```
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To connect OpenOCD (https://github.com/SpinalHDL/openocd_riscv) to the simulation :
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```sh
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src/openocd -f tcl/interface/jtag_tcp.cfg -c "set MURAX_CPU0_YAML /home/spinalvm/Spinal/VexRiscv/cpu0.yaml" -f tcl/target/murax.cfg
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```
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You can find multiples software examples and demo there : https://github.com/SpinalHDL/VexRiscvSocSoftware/tree/master/projects/murax
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There is some measurements of Murax SoC timings and area :
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```
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Murax interlocked stages (0.37 DMIPS/Mhz) ->
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Artix 7 -> 306 Mhz 1021 LUT 1291 FF
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Cyclone V -> 173 Mhz 752 ALMs
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Cyclone IV -> 140 Mhz 1483 LUT 1,250 FF
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Cyclone II -> 127 Mhz 1484 LUT 1,249 FF
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ICE40-HX -> 51 Mhz 2387 LC (icestorm)
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MuraxFast bypassed stages (0.55 DMIPS/Mhz) ->
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Artix 7 -> 310 Mhz 1192 LUT 1388 FF
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Cyclone V -> 160 Mhz 893 ALMs
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Cyclone IV -> 142 Mhz 1726 LUT 1,284 FF
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Cyclone II -> 106 Mhz 1714 LUT 1,283 FF
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ICE40-HX -> 45 Mhz, 2718 LC (icestorm)
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```
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There is some scripts to generate the SoC and call the icestorm toolchain there : scripts/Murax/
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## Build the RISC-V GCC
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In fact, now you can find some prebuild GCC : <br>
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- https://www.sifive.com/products/tools/ => SiFive GNU Embedded Toolchain
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The VexRiscvSocSoftware makefiles are expecting to find this prebuild version in /opt/riscv/__contentOfThisPreBuild__
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```sh
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wget https://static.dev.sifive.com/dev-tools/riscv64-unknown-elf-gcc-20170612-x86_64-linux-centos6.tar.gz
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tar -xzvf riscv64-unknown-elf-gcc-20170612-x86_64-linux-centos6.tar.gz
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sudo mv riscv64-unknown-elf-gcc-20170612-x86_64-linux-centos6 /opt/riscv64-unknown-elf-gcc-20170612-x86_64-linux-centos6
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sudo mv /opt/riscv64-unknown-elf-gcc-20170612-x86_64-linux-centos6 /opt/riscv
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echo 'export PATH=/opt/riscv/bin:$PATH' >> ~/.bashrc
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```
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But if you want to compile from sources in /opt/ the rv32i and rv32im gcc, do the following (will take hours):
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```sh
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# Be carefull, sometime the git clone has issue to successfully clone riscv-gnu-toolchain.
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sudo apt-get install autoconf automake autotools-dev curl libmpc-dev libmpfr-dev libgmp-dev gawk build-essential bison flex texinfo gperf libtool patchutils bc zlib1g-dev -y
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git clone --recursive https://github.com/riscv/riscv-gnu-toolchain riscv-gnu-toolchain
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cd riscv-gnu-toolchain
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echo "Starting RISC-V Toolchain build process"
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ARCH=rv32im
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rmdir -rf $ARCH
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mkdir $ARCH; cd $ARCH
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../configure --prefix=/opt/$ARCH --with-arch=$ARCH --with-abi=ilp32
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sudo make -j4
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cd ..
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ARCH=rv32i
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rmdir -rf $ARCH
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mkdir $ARCH; cd $ARCH
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../configure --prefix=/opt/$ARCH --with-arch=$ARCH --with-abi=ilp32
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sudo make -j4
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cd ..
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echo -e "\\nRISC-V Toolchain installation completed!"
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```
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## CPU parametrization and instantiation example
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You can find many example of different config in the https://github.com/SpinalHDL/VexRiscv/tree/master/src/main/scala/vexriscv/demo folder. There is one :
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```scala
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import vexriscv._
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import vexriscv.plugin._
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//Instanciate one VexRiscv
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val cpu = new VexRiscv(
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//Provide a configuration instance
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config = VexRiscvConfig(
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//Provide a list of plugins which will futher add their logic into the CPU
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plugins = List(
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new PcManagerSimplePlugin(
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resetVector = 0x00000000l,
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relaxedPcCalculation = true
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),
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new IBusSimplePlugin(
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interfaceKeepData = false,
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catchAccessFault = false
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),
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new DBusSimplePlugin(
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catchAddressMisaligned = false,
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catchAccessFault = false
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),
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new DecoderSimplePlugin(
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catchIllegalInstruction = false
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),
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new RegFilePlugin(
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regFileReadyKind = Plugin.SYNC,
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zeroBoot = true
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),
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new IntAluPlugin,
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new SrcPlugin(
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separatedAddSub = false,
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executeInsertion = false
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),
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new LightShifterPlugin,
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new HazardSimplePlugin(
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bypassExecute = false,
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bypassMemory = false,
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bypassWriteBack = false,
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bypassWriteBackBuffer = false
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),
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new BranchPlugin(
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earlyBranch = false,
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catchAddressMisaligned = false,
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prediction = NONE
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),
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new YamlPlugin("cpu0.yaml")
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)
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)
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)
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```
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## Add a custom instruction to the CPU via the plugin system
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There is an example of an simple plugin which add an simple SIMD_ADD instruction :
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```scala
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import spinal.core._
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import vexriscv.plugin.Plugin
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import vexriscv.{Stageable, DecoderService, VexRiscv}
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//This plugin example will add a new instruction named SIMD_ADD which do the following :
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//
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//RD : Regfile Destination, RS : Regfile Source
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//RD( 7 downto 0) = RS1( 7 downto 0) + RS2( 7 downto 0)
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//RD(16 downto 8) = RS1(16 downto 8) + RS2(16 downto 8)
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//RD(23 downto 16) = RS1(23 downto 16) + RS2(23 downto 16)
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//RD(31 downto 24) = RS1(31 downto 24) + RS2(31 downto 24)
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//
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//Instruction encoding :
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//0000011----------000-----0110011
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// |RS2||RS1| |RD |
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//
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//Note : RS1, RS2, RD positions follow the RISC-V spec and are common for all instruction of the ISA
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class SimdAddPlugin extends Plugin[VexRiscv]{
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//Define the concept of IS_SIMD_ADD signals, which specify if the current instruction is destined for ths plugin
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object IS_SIMD_ADD extends Stageable(Bool)
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//Callback to setup the plugin and ask for different services
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override def setup(pipeline: VexRiscv): Unit = {
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import pipeline.config._
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//Retrieve the DecoderService instance
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val decoderService = pipeline.service(classOf[DecoderService])
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//Specify the IS_SIMD_ADD default value when instruction are decoded
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decoderService.addDefault(IS_SIMD_ADD, False)
|
|
|
|
//Specify the instruction decoding which should be applied when the instruction match the 'key' parttern
|
|
decoderService.add(
|
|
//Bit pattern of the new SIMD_ADD instruction
|
|
key = M"0000011----------000-----0110011",
|
|
|
|
//Decoding specification when the 'key' pattern is recognized in the instruction
|
|
List(
|
|
IS_SIMD_ADD -> True,
|
|
REGFILE_WRITE_VALID -> True, //Enable the register file write
|
|
BYPASSABLE_EXECUTE_STAGE -> True, //Notify the hazard management unit that the instruction result is already accessible in the EXECUTE stage (Bypass ready)
|
|
BYPASSABLE_MEMORY_STAGE -> True, //Same as above but for the memory stage
|
|
RS1_USE -> True, //Notify the hazard management unit that this instruction use the RS1 value
|
|
RS2_USE -> True //Same than above but for RS2.
|
|
)
|
|
)
|
|
}
|
|
|
|
override def build(pipeline: VexRiscv): Unit = {
|
|
import pipeline._
|
|
import pipeline.config._
|
|
|
|
//Add a new scope on the execute stage (used to give a name to signals)
|
|
execute plug new Area {
|
|
//Define some signals used internally to the plugin
|
|
val rs1 = execute.input(RS1).asUInt
|
|
//32 bits UInt value of the regfile[RS1]
|
|
val rs2 = execute.input(RS2).asUInt
|
|
val rd = UInt(32 bits)
|
|
|
|
//Do some computation
|
|
rd(7 downto 0) := rs1(7 downto 0) + rs2(7 downto 0)
|
|
rd(16 downto 8) := rs1(16 downto 8) + rs2(16 downto 8)
|
|
rd(23 downto 16) := rs1(23 downto 16) + rs2(23 downto 16)
|
|
rd(31 downto 24) := rs1(31 downto 24) + rs2(31 downto 24)
|
|
|
|
//When the instruction is a SIMD_ADD one, then write the result into the register file data path.
|
|
when(execute.input(IS_SIMD_ADD)) {
|
|
execute.output(REGFILE_WRITE_DATA) := rd.asBits
|
|
}
|
|
}
|
|
}
|
|
}
|
|
```
|
|
|
|
Then if you want to add this plugin to a given CPU, you just need to add it in its parameterized plugin list.
|
|
|
|
This example is a very simple one, but each plugin can really have access to the whole CPU
|
|
- Halt a given stage of the CPU
|
|
- Unschedule instructions
|
|
- Emit an exception
|
|
- Introduce new instruction decoding specification
|
|
- Ask to jump the PC somewhere
|
|
- Read signals published by other plugins
|
|
- override published signals values
|
|
- Provide an alternative implementation
|
|
- ...
|
|
|
|
As a demonstrator, this SimdAddPlugin was integrated in the src/main/scala/vexriscv/demo/GenCustomSimdAdd.scala CPU configuration and is self tested by the src/test/cpp/custom/simd_add application by running the following commands :
|
|
|
|
```sh
|
|
# Generate the CPU
|
|
sbt "run-main vexriscv.demo.GenCustomSimdAdd"
|
|
|
|
cd src/test/cpp/regression/
|
|
|
|
# Optionally add TRACE=yes if you want to get the VCD waveform from the simulation.
|
|
# Also you have to know that by default, the testbench introduce instruction/data bus stall.
|
|
# Note the CUSTOM_SIMD_ADD flag is set to yes.
|
|
make clean run IBUS=SIMPLE DBUS=SIMPLE CSR=no MMU=no DEBUG_PLUGIN=no MUL=no DIV=no DHRYSTONE=no REDO=2 CUSTOM_SIMD_ADD=yes
|
|
```
|
|
|
|
To retrieve the plugin related signals in the wave, just filter with `simd`.
|
|
|
|
## CPU clock and resets
|
|
|
|
Without the debug plugin, the CPU will have `clk` input and a `reset` input, which is very standard. But with the debug plugin the situation is the following :
|
|
|
|
- clk : As before, the clock which drive the whole CPU design, including the debug logic
|
|
- reset : Reset all the CPU states excepted the debug logics
|
|
- debugReset : Reset the debug logic of the CPU
|
|
- debug_resetOut : It is a CPU output signal which allow the JTAG to reset the CPU + the memory interconnect + the peripherals
|
|
|
|
So there is the reset interconnect in case you use the debug plugin :
|
|
|
|
```
|
|
VexRiscv
|
|
+------------------+
|
|
| |
|
|
toplevelReset >----+--------> debugReset |
|
|
| | |
|
|
| +-----< debug_resetOut |
|
|
| | | |
|
|
+--or>-+-> reset |
|
|
| | |
|
|
| +------------------+
|
|
|
|
|
+-> Interconnect / Peripherals
|
|
```
|