Dolu1990 7c19288648 Update Synthesis bench ... Update some synthesis results		2017-11-17 20:10:46 +01:00
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ressource/hex	Move CPU and UART configs into the murax configuration object (in place of toplevel hardcoding)	2017-08-04 14:55:54 +02:00
scala/vexriscv	Update Synthesis bench	2017-11-17 20:10:46 +01:00