Hardware
/
VexRiscv
mirror of https://github.com/SpinalHDL/VexRiscv.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
A FPGA friendly 32 bit RISC-V CPU implementation
15 Commits 39 Branches 2 Tags 15 MiB
Assembly 62%
Scala 26.9%
C++ 4.7%
C 3.8%
Tcl 1.2%
Other 1.3%
Go to file
Charles Papon c6610ea454 Fix halt arbitrations 2017-03-15 17:14:58 +01:00
project
…
src Fix halt arbitrations 2017-03-15 17:14:58 +01:00
.gitignore Pass verilator simple literal, add, jump 2017-03-12 20:12:40 +01:00
README.md
…
backup
…
build.sbt
…

README.md

WIP