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VexRiscv
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A FPGA friendly 32 bit RISC-V CPU implementation
cpu
fpga
riscv
soc
softcore
spinalhdl
verilog
vhdl
33
Commits
39
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2
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15
MiB
Assembly
62%
Scala
26.9%
C++
4.7%
C
3.8%
Tcl
1.2%
Other
1.3%
de4c2470c8
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Charles Papon
de4c2470c8
MachineCsr add mcycle and minstret
2017-03-22 20:38:43 +01:00
project
boot
2017-03-08 22:17:48 +01:00
src
MachineCsr add mcycle and minstret
2017-03-22 20:38:43 +01:00
.gitignore
Add self checked dhrystone test
2017-03-18 12:32:14 +01:00
README.md
boot
2017-03-08 22:17:48 +01:00
backup
boot
2017-03-08 22:17:48 +01:00
build.sbt
WIP
2017-03-11 00:34:49 +01:00
README.md
WIP