Hardware
/
VexRiscv
mirror of https://github.com/SpinalHDL/VexRiscv.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
A FPGA friendly 32 bit RISC-V CPU implementation
10 Commits 39 Branches 2 Tags 15 MiB
Assembly 62%
Scala 26.9%
C++ 4.7%
C 3.8%
Tcl 1.2%
Other 1.3%
Go to file
Charles Papon df99a0d963 Better decoding 2017-03-13 18:30:37 +01:00
project boot 2017-03-08 22:17:48 +01:00
src Better decoding 2017-03-13 18:30:37 +01:00
.gitignore Pass verilator simple literal, add, jump 2017-03-12 20:12:40 +01:00
README.md boot 2017-03-08 22:17:48 +01:00
backup boot 2017-03-08 22:17:48 +01:00
build.sbt WIP 2017-03-11 00:34:49 +01:00

README.md

WIP