Hardware/VexRiscv
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A FPGA friendly 32 bit RISC-V CPU implementation
2 commits 39 branches 2 tags 15 MiB
Assembly 62%
Scala 26.9%
C++ 4.7%
C 3.8%
Tcl 1.2%
Other 1.3%
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Dolu1990 fc7e9a7730 wip
2017-03-09 01:07:55 +01:00
project boot 2017-03-08 22:17:48 +01:00
src/main/scala/SpinalRiscv wip 2017-03-09 01:07:55 +01:00
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README.md

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