Hardware/VexRiscv
1
0
Fork 0
mirror of https://github.com/SpinalHDL/VexRiscv.git synced 2025-01-03 03:43:39 -05:00
Code Issues Projects Releases Packages Wiki Activity
A FPGA friendly 32 bit RISC-V CPU implementation
3 commits 39 branches 2 tags 15 MiB
Assembly 62%
Scala 26.9%
C++ 4.7%
C 3.8%
Tcl 1.2%
Other 1.3%
Find a file
Dolu1990 fcb70a333f WIP
2017-03-11 00:34:49 +01:00
project boot 2017-03-08 22:17:48 +01:00
src/main/scala/SpinalRiscv WIP 2017-03-11 00:34:49 +01:00
.gitignore boot 2017-03-08 22:17:48 +01:00
backup boot 2017-03-08 22:17:48 +01:00
build.sbt WIP 2017-03-11 00:34:49 +01:00
README.md boot 2017-03-08 22:17:48 +01:00

README.md

WIP