41 lines
1.3 KiB
Plaintext
41 lines
1.3 KiB
Plaintext
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# Input clock 100 MHz
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create_clock -period 10 clk100_ibuf -waveform {0.000 5.000}
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# Input clock BUFG 100 MHz
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create_clock -period 10 soc_clk100bg -waveform {0.000 5.000}
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# PLL feedback loop 100 MHz
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create_clock -period 10 soc_pll_fb -waveform {0.000 5.000}
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# PLL CLKOUT0 60 MHz
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create_clock -period 16.666 soc_pll_sys -waveform {0.000 8.333}
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# BUFG CLKOUT0 60 MHz
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create_clock -period 16.666 sys_clk -waveform {0.000 8.333}
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# PLL CLKOUT1 240 MHz
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create_clock -period 4.166 soc_pll_sys4x -waveform {0.000 2.083}
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# BUFG CLKOUT1 240 MHz
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create_clock -period 4.166 sys4x_clk -waveform {0.000 2.083}
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# PLL CLKOUT2 240 MHz
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create_clock -period 4.166 soc_pll_sys4x_dqs -waveform {1.041 3.124}
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# BUFG CLKOUT2 240 MHz
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create_clock -period 4.166 sys4x_dqs_clk -waveform {1.041 3.124}
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# PLL CLKOUT3 200 MHz
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create_clock -period 5 soc_pll_clk200 -waveform {0.000 2.500}
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# BUFG CLKOUT3 200 MHz
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create_clock -period 5 clk200_clk -waveform {0.000 2.500}
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# PLL CLKOUT4 25 MHz
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create_clock -period 40 soc_pll_clk100 -waveform {0.000 20.000}
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# BUFG CLKOUT4 25 MHz
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create_clock -period 40 eth_ref_clk_obuf -waveform {0.000 20.000}
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set_clock_groups -exclusive -group {clk100 soc_clk100bg soc_pll_fb} -group {soc_pll_sys sys_clk} -group {soc_pll_sys4x soc_pll_sys4x_dqs} -group {soc_pll_clk200 clk200_clk}
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