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f4pga-examples
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Add sdc files to examples 

Signed-off-by: Joanna Brozek <jbrozek@antmicro.com>
This commit is contained in:
Joanna Brozek 2020-04-23 12:59:27 +02:00
parent fcb1cb0032
commit 4fa99d24a7
6 changed files with 55 additions and 10 deletions
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9
counter_test/Makefile
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@ -5,7 +5,8 @@ VERILOG:=${current_dir}/counter_basys3.v
PARTNAME:= xc7a35tcpg236-1
DEVICE := xc7a50t_test
BITSTREAM_DEVICE := artix7
PCF=${current_dir}/basys3.pcf
PCF:=${current_dir}/basys3.pcf
SDC:=${current_dir}/basys3.sdc
BUILDDIR:=build
all: ${BUILDDIR}/${TOP}.bit
@ -17,13 +18,13 @@ ${BUILDDIR}/${TOP}.eblif: | ${BUILDDIR}
cd ${BUILDDIR} && synth -t ${TOP} -v ${VERILOG} -d ${BITSTREAM_DEVICE} -p ${PARTNAME}
${BUILDDIR}/${TOP}.net: ${BUILDDIR}/${TOP}.eblif
cd ${BUILDDIR} && pack -e ${TOP}.eblif -d ${DEVICE}
cd ${BUILDDIR} && pack -e ${TOP}.eblif -d ${DEVICE} -s ${SDC}
${BUILDDIR}/${TOP}.place: ${BUILDDIR}/${TOP}.net
cd ${BUILDDIR} && place -e ${TOP}.eblif -d ${DEVICE} -p ${PCF} -n ${TOP}.net -P ${PARTNAME} 2>&1 > /dev/null
cd ${BUILDDIR} && place -e ${TOP}.eblif -d ${DEVICE} -p ${PCF} -n ${TOP}.net -P ${PARTNAME} -s ${SDC} 2>&1 > /dev/null
${BUILDDIR}/${TOP}.route: ${BUILDDIR}/${TOP}.place
cd ${BUILDDIR} && route -e ${TOP}.eblif -d ${DEVICE} 2>&1 > /dev/null
cd ${BUILDDIR} && route -e ${TOP}.eblif -d ${DEVICE} -s ${SDC} 2>&1 > /dev/null
${BUILDDIR}/${TOP}.fasm: ${BUILDDIR}/${TOP}.route
cd ${BUILDDIR} && write_fasm -e ${TOP}.eblif -d ${DEVICE}

1
counter_test/basys3.sdc Normal file
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@ -0,0 +1 @@
create_clock -period 10 bufg

7
linux_litex_demo/Makefile
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@ -10,6 +10,7 @@ PARTNAME := xc7a35tcsg324-1
DEVICE := xc7a50t_test
BITSTREAM_DEVICE := artix7
PCF := ${current_dir}/arty.pcf
SDC := ${current_dir}/arty.sdc
BUILDDIR := build
all: ${BUILDDIR}/${TOP}.bit
@ -22,13 +23,13 @@ ${BUILDDIR}/${TOP}.eblif: | ${BUILDDIR}
cd ${BUILDDIR} && synth -t ${TOP} -v ${VERILOG} -d ${BITSTREAM_DEVICE} -p ${PARTNAME} 2>&1 > /dev/null
${BUILDDIR}/${TOP}.net: ${BUILDDIR}/${TOP}.eblif
cd ${BUILDDIR} && pack -e ${TOP}.eblif -d ${DEVICE} 2>&1 > /dev/null
cd ${BUILDDIR} && pack -e ${TOP}.eblif -d ${DEVICE} -s ${SDC} 2>&1 > /dev/null
${BUILDDIR}/${TOP}.place: ${BUILDDIR}/${TOP}.net
cd ${BUILDDIR} && place -e ${TOP}.eblif -d ${DEVICE} -p ${PCF} -n ${TOP}.net -P ${PARTNAME} 2>&1 > /dev/null
cd ${BUILDDIR} && place -e ${TOP}.eblif -d ${DEVICE} -p ${PCF} -n ${TOP}.net -P ${PARTNAME} -s ${SDC} 2>&1 > /dev/null
${BUILDDIR}/${TOP}.route: ${BUILDDIR}/${TOP}.place
cd ${BUILDDIR} && route -e ${TOP}.eblif -d ${DEVICE} 2>&1 > /dev/null
cd ${BUILDDIR} && route -e ${TOP}.eblif -d ${DEVICE} -s ${SDC} 2>&1 > /dev/null
${BUILDDIR}/${TOP}.fasm: ${BUILDDIR}/${TOP}.route
cd ${BUILDDIR} && write_fasm -e ${TOP}.eblif -d ${DEVICE}

40
linux_litex_demo/arty.sdc Normal file
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@ -0,0 +1,40 @@
# Input clock 100 MHz
create_clock -period 10 clk100_ibuf -waveform {0.000 5.000}
# Input clock BUFG 100 MHz
create_clock -period 10 soc_clk100bg -waveform {0.000 5.000}
# PLL feedback loop 100 MHz
create_clock -period 10 soc_pll_fb -waveform {0.000 5.000}
# PLL CLKOUT0 60 MHz
create_clock -period 16.666 soc_pll_sys -waveform {0.000 8.333}
# BUFG CLKOUT0 60 MHz
create_clock -period 16.666 sys_clk -waveform {0.000 8.333}
# PLL CLKOUT1 240 MHz
create_clock -period 4.166 soc_pll_sys4x -waveform {0.000 2.083}
# BUFG CLKOUT1 240 MHz
create_clock -period 4.166 sys4x_clk -waveform {0.000 2.083}
# PLL CLKOUT2 240 MHz
create_clock -period 4.166 soc_pll_sys4x_dqs -waveform {1.041 3.124}
# BUFG CLKOUT2 240 MHz
create_clock -period 4.166 sys4x_dqs_clk -waveform {1.041 3.124}
# PLL CLKOUT3 200 MHz
create_clock -period 5 soc_pll_clk200 -waveform {0.000 2.500}
# BUFG CLKOUT3 200 MHz
create_clock -period 5 clk200_clk -waveform {0.000 2.500}
# PLL CLKOUT4 25 MHz
create_clock -period 40 soc_pll_clk100 -waveform {0.000 20.000}
# BUFG CLKOUT4 25 MHz
create_clock -period 40 eth_ref_clk_obuf -waveform {0.000 20.000}
set_clock_groups -exclusive -group {clk100 soc_clk100bg soc_pll_fb} -group {soc_pll_sys sys_clk} -group {soc_pll_sys4x soc_pll_sys4x_dqs} -group {soc_pll_clk200 clk200_clk}

7
picosoc_demo/Makefile
View File

@ -10,6 +10,7 @@ PARTNAME := xc7a35tcpg236-1
DEVICE := xc7a50t_test
BITSTREAM_DEVICE := artix7
PCF := ${current_dir}/basys3.pcf
SDC := ${current_dir}/basys3.sdc
BUILDDIR := build
all: ${BUILDDIR}/${TOP}.bit
@ -21,13 +22,13 @@ ${BUILDDIR}/${TOP}.eblif: | ${BUILDDIR}
cd ${BUILDDIR} && synth -t ${TOP} -v ${VERILOG} -d ${BITSTREAM_DEVICE} -p ${PARTNAME} 2>&1 > /dev/null
${BUILDDIR}/${TOP}.net: ${BUILDDIR}/${TOP}.eblif
cd ${BUILDDIR} && pack -e ${TOP}.eblif -d ${DEVICE} 2>&1 > /dev/null
cd ${BUILDDIR} && pack -e ${TOP}.eblif -d ${DEVICE} -s ${SDC} 2>&1 > /dev/null
${BUILDDIR}/${TOP}.place: ${BUILDDIR}/${TOP}.net
cd ${BUILDDIR} && place -e ${TOP}.eblif -d ${DEVICE} -p ${PCF} -n ${TOP}.net -P ${PARTNAME} 2>&1 > /dev/null
cd ${BUILDDIR} && place -e ${TOP}.eblif -d ${DEVICE} -p ${PCF} -n ${TOP}.net -P ${PARTNAME} -s ${SDC} 2>&1 > /dev/null
${BUILDDIR}/${TOP}.route: ${BUILDDIR}/${TOP}.place
cd ${BUILDDIR} && route -e ${TOP}.eblif -d ${DEVICE} 2>&1 > /dev/null
cd ${BUILDDIR} && route -e ${TOP}.eblif -d ${DEVICE} -s ${SDC} 2>&1 > /dev/null
${BUILDDIR}/${TOP}.fasm: ${BUILDDIR}/${TOP}.route
cd ${BUILDDIR} && write_fasm -e ${TOP}.eblif -d ${DEVICE}

1
picosoc_demo/basys3.sdc Normal file
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@ -0,0 +1 @@
create_clock -period 10 clk_bufg