34 lines
1.4 KiB
Markdown
34 lines
1.4 KiB
Markdown
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# F4PGA examples
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<p align="center">
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<a title="GitHub Actions" href="https://github.com/chipsalliance/f4pga-examples/actions"><img src="https://github.com/chipsalliance/f4pga-examples/workflows/doc-test/badge.svg?branch=master"></a><!--
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-->
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<a title="Documentation Status" href="https://f4pga-examples.readthedocs.io/en/latest/?badge=latest"><img alt="'Doc' workflow status" src="https://readthedocs.org/projects/f4pga-examples/badge/?version=latest"></a><!--
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-->
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</p>
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This repository provides example FPGA designs that can be built using the F4PGA open source toolchain.
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These examples target the Xilinx 7-Series and the QuickLogic EOS S3 devices.
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Please refer to the [project documentation](https://f4pga-examples.readthedocs.io) for a proper guide on how to run
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these examples as well as instructions on how to build and compile your own HDL designs using the F4PGA toolchain.
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The repository includes:
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* [xc7/](./xc7) and [eos-s3/](./eos-s3) - Examples for Xilinx 7-Series and EOS-S3 devices, including:
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* Verilog code
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* Pin constraints files
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* Timing constraints files
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* Makefiles for running the F4PGA toolchain
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* [docs/](./docs) - Guide on how to get started with F4PGA and build provided examples
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* [.github/](./.github) - Directory with CI configuration and scripts
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The examples provided in this repository are automatically built and tested in CI by extracting necessary code snippets
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with [tuttest](https://github.com/antmicro/tuttest).
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