33 lines
679 B
Systemverilog
33 lines
679 B
Systemverilog
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`timescale 1ns / 1ps
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`default_nettype none
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module timer_par #(parameter MOD_VALUE=1, parameter BIT_WIDTH = 1) (
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input wire logic clk, reset, increment,
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output logic rolling_over,
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output logic[BIT_WIDTH-1:0] count
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);
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always_ff @(posedge clk)
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begin
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if(reset)
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count <= 0;
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else if(increment)
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begin
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if(rolling_over)
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count <= 0;
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else
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count <= count + 1'b1;
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end
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end
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always_comb
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begin
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if(increment && (count==MOD_VALUE-1))
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rolling_over = 1'b1;
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else
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rolling_over = 1'b0;
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end
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endmodule
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