14 lines
180 B
Verilog
14 lines
180 B
Verilog
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module top (
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input wire clk,
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output wire [3:0] led
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);
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reg [3:0] cnt;
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initial cnt <= 0;
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always @(posedge clk) cnt <= cnt + 1;
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assign led = cnt;
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endmodule
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