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Ran PWM and timer through verible formatter and linter 

Signed-off-by: Joshua Fife <jpfife17@gmail.com>
This commit is contained in:
Joshua Fife 2021-08-11 17:08:41 -06:00
parent a6cda9b405
commit 4b054b5496
11 changed files with 210 additions and 159 deletions
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2
xc7/pulse_width_led/Makefile
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@ -2,7 +2,7 @@ mkfile_path := $(abspath $(lastword $(MAKEFILE_LIST)))
current_dir := $(patsubst %/,%,$(dir $(mkfile_path)))
TOP := top
VERILOG := ${current_dir}/PWM.v
VERILOG += ${current_dir}/PWM_top.v
VERILOG += ${current_dir}/pulse_led.v
DEVICE := xc7a50t_test
BITSTREAM_DEVICE := artix7
BUILDDIR := build

23
xc7/pulse_width_led/PWM.v
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@ -1,17 +1,14 @@
module PWM(
input wire clk,
input wire [13:0] width,
output reg pulse
module PWM (
input wire clk,
input wire [13:0] width,
output reg pulse
);
reg[13:0] counter = 0;
reg [13:0] counter = 0;
always @(posedge clk)
begin
counter <= counter + 1;
if(counter < width)
pulse <= 1'b1;
else
pulse <= 1'b0;
end
always @(posedge clk) begin
counter <= counter + 1;
if (counter < width) pulse <= 1'b1;
else pulse <= 1'b0;
end
endmodule

18
xc7/pulse_width_led/PWM_top.v
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@ -1,18 +0,0 @@
module top(
input wire clk,
input wire [3:0] sw,
input wire [3:0] btn,
output wire pulse_red, pulse_blue, pulse_green
);
wire [13:0] pulse_wideR, pulse_wideB, pulse_wideG;
assign pulse_wideR = {1'b0, sw[3:1], 10'd0};
assign pulse_wideG = {1'b0, sw[0], btn[3:2], 10'd0};
assign pulse_wideB = {btn[1:0], 11'd0};
PWM R0(.clk(clk), .pulse(pulse_red), .width(pulse_wideR));
PWM B0(.clk(clk), .pulse(pulse_green), .width(pulse_wideB));
PWM G0(.clk(clk), .pulse(pulse_blue), .width(pulse_wideG));
endmodule

32
xc7/pulse_width_led/pulse_led.v Normal file
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@ -0,0 +1,32 @@
module top (
input wire clk,
input wire [3:0] sw,
input wire [3:0] btn,
output wire pulse_red,
pulse_blue,
pulse_green
);
wire [13:0] pulse_wideR, pulse_wideB, pulse_wideG;
assign pulse_wideR = {1'b0, sw[3:1], 10'd0};
assign pulse_wideG = {1'b0, sw[0], btn[3:2], 10'd0};
assign pulse_wideB = {btn[1:0], 11'd0};
PWM R0 (
.clk (clk),
.pulse(pulse_red),
.width(pulse_wideR)
);
PWM B0 (
.clk (clk),
.pulse(pulse_green),
.width(pulse_wideB)
);
PWM G0 (
.clk (clk),
.pulse(pulse_blue),
.width(pulse_wideG)
);
endmodule

31
xc7/timer/clock.sv Normal file
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@ -0,0 +1,31 @@
`timescale 1ns / 1ps `default_nettype none
module top (
input wire logic clk,
btnc,
sw,
output logic [3:0] anode,
output logic [7:0] segment
);
logic [15:0] digitData;
timer TC0 (
clk,
btnc,
sw,
digitData[3:0],
digitData[7:4],
digitData[11:8],
digitData[15:12]
);
display_control SSC0 (
clk,
btnc,
digitData,
4'b1111,
4'b0100,
anode,
segment
);
endmodule

66
xc7/timer/SSControl.sv → xc7/timer/display_control.sv
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@ -1,54 +1,52 @@
`default_nettype none
module SevenSegmentControl(
input wire logic clk,
input wire logic reset,
input wire logic [15:0] dataIn,
input wire logic [3:0] digitDisplay,
input wire logic [3:0] digitPoint,
output logic [3:0] anode,
output logic [7:0] segment
);
module display_control (
input wire logic clk,
input wire logic reset,
input wire logic [15:0] dataIn,
input wire logic [ 3:0] digitDisplay,
input wire logic [ 3:0] digitPoint,
output logic [ 3:0] anode,
output logic [ 7:0] segment
);
parameter integer COUNT_BITS = 17;
logic [COUNT_BITS-1:0] count_val;
logic [1:0] anode_select;
logic [3:0] cur_anode;
logic [3:0] cur_data_in;
always_ff @(posedge clk) begin
if (reset)
count_val <= 0;
else
count_val <= count_val + 1;
end
parameter integer COUNT_BITS = 17;
assign anode_select = count_val[COUNT_BITS-1:COUNT_BITS-2];
logic [COUNT_BITS-1:0] count_val;
logic [ 1:0] anode_select;
logic [ 3:0] cur_anode;
logic [ 3:0] cur_data_in;
assign cur_anode =
always_ff @(posedge clk) begin
if (reset) count_val <= 0;
else count_val <= count_val + 1;
end
assign anode_select = count_val[COUNT_BITS-1:COUNT_BITS-2];
assign cur_anode =
(anode_select == 2'b00) ? 4'b1110 :
(anode_select == 2'b01) ? 4'b1101 :
(anode_select == 2'b10) ? 4'b1011 :
4'b0111;
assign anode = cur_anode | (~digitDisplay);
assign cur_data_in =
assign anode = cur_anode | (~digitDisplay);
assign cur_data_in =
(anode_select == 2'b00) ? dataIn[3:0] :
(anode_select == 2'b01) ? dataIn[7:4] :
(anode_select == 2'b10) ? dataIn[11:8] :
dataIn[15:12] ;
assign segment[7] =
assign segment[7] =
(anode_select == 2'b00) ? ~digitPoint[0] :
(anode_select == 2'b01) ? ~digitPoint[1] :
(anode_select == 2'b10) ? ~digitPoint[2] :
~digitPoint[3] ;
assign segment[6:0] =
assign segment[6:0] =
(cur_data_in == 0) ? 7'b1000000 :
(cur_data_in == 1) ? 7'b1111001 :
(cur_data_in == 2) ? 7'b0100100 :
@ -66,5 +64,5 @@ module SevenSegmentControl(
(cur_data_in == 14) ? 7'b0000110 :
7'b0001110;
endmodule
endmodule

56
xc7/timer/modify_count.sv
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@ -1,30 +1,26 @@
`default_nettype none
module mod_counter #(parameter MOD_VALUE=10) (
input wire logic clk, reset, increment,
output logic rolling_over,
output logic[3:0] count = 0
);
always_ff @(posedge clk)
begin
if(reset)
count <= 4'b0000;
else if(increment)
begin
if(rolling_over)
count <= 4'b0000;
else
count <= count + 4'b0001;
end
end
always_comb
begin
if(increment && (count==MOD_VALUE-1))
rolling_over = 1'b1;
else
rolling_over = 1'b0;
end
endmodule
`default_nettype none
module modify_count #(
parameter MOD_VALUE = 10
) (
input wire logic clk,
reset,
increment,
output logic rolling_over,
output logic [3:0] count = 0
);
always_ff @(posedge clk) begin
if (reset) count <= 4'b0000;
else if (increment) begin
if (rolling_over) count <= 4'b0000;
else count <= count + 4'b0001;
end
end
always_comb begin
if (increment && (count == MOD_VALUE - 1)) rolling_over = 1'b1;
else rolling_over = 1'b0;
end
endmodule

19
xc7/timer/stwatch.sv
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@ -1,19 +0,0 @@
`timescale 1ns / 1ps
`default_nettype none
module stopwatch(
input wire logic clk, reset, run,
output logic[3:0] digit0, digit1, digit2, digit3
);
logic inc0, inc1, inc2, inc3, inc4;
logic[23:0] timerCount;
mod_counter #(10) M0(clk, reset, inc0, inc1, digit0);
mod_counter #(10) M1(clk, reset, inc1, inc2, digit1);
mod_counter #(10) M2(clk, reset, inc2, inc3, digit2);
mod_counter #(6) M3(clk, reset, inc3, inc4, digit3);
timer #(1000000) T0(clk, reset, run, inc0, timerCount);
endmodule

27
xc7/timer/time_counter.sv Normal file
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@ -0,0 +1,27 @@
`timescale 1ns / 1ps `default_nettype none
module time_counter #(
parameter MOD_VALUE = 1000000
) (
input wire logic clk,
reset,
increment,
output logic rolling_over,
output logic [23:0] count = 0
);
always_ff @(posedge clk) begin
if (reset) count <= 0;
else if (increment) begin
if (rolling_over) count <= 0;
else count <= count + 1'b1;
end
end
always_comb begin
if (increment && (count == MOD_VALUE - 1)) rolling_over = 1'b1;
else rolling_over = 1'b0;
end
endmodule

81
xc7/timer/timer.sv
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@ -1,32 +1,53 @@
`timescale 1ns / 1ps
`default_nettype none
`timescale 1ns / 1ps `default_nettype none
module timer #(parameter MOD_VALUE=1000000) (
input wire logic clk, reset, increment,
output logic rolling_over,
output logic[23:0] count = 0
);
always_ff @(posedge clk)
begin
if(reset)
count <= 0;
else if(increment)
begin
if(rolling_over)
count <= 0;
else
count <= count + 1'b1;
end
end
always_comb
begin
if(increment && (count==MOD_VALUE-1))
rolling_over = 1'b1;
else
rolling_over = 1'b0;
end
module timer (
input wire logic clk,
reset,
run,
output logic [3:0] digit0,
digit1,
digit2,
digit3
);
logic inc0, inc1, inc2, inc3, inc4;
logic [23:0] timerCount;
modify_count #(10) M0 (
clk,
reset,
inc0,
inc1,
digit0
);
modify_count #(10) M1 (
clk,
reset,
inc1,
inc2,
digit1
);
modify_count #(10) M2 (
clk,
reset,
inc2,
inc3,
digit2
);
modify_count #(6) M3 (
clk,
reset,
inc3,
inc4,
digit3
);
time_counter #(1000000) T0 (
clk,
reset,
run,
inc0,
timerCount
);
endmodule

14
xc7/timer/timer_top.sv
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@ -1,14 +0,0 @@
`timescale 1ns / 1ps
`default_nettype none
module top(
input wire logic clk, btnc, sw,
output logic[3:0] anode,
output logic[7:0] segment
);
logic[15:0] digitData;
stopwatch SW0(clk, btnc, sw, digitData[3:0], digitData[7:4], digitData[11:8], digitData[15:12]);
SevenSegmentControl SSC0(clk, btnc, digitData, 4'b1111 , 4'b0100 , anode, segment);
endmodule