Added extra XDC PCF SDC info
Signed-off-by: Joshua Fife <jpfife17@gmail.com>
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Joshua Fife
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@ -4,7 +4,7 @@ A key steep in creating your own designs is understanding how to use the Makefil
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Example
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-------
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To understand how the Makfiles within symbiflow are setup lets take a look at a more simple Makefile that will run the symbiflow counter test on the basys3 board. Highlighted lines within the code bellow are of particular interest and will change depending on your design and hardware.
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To understand how the Makfiles within symbiflow are setup, lets take a look at a more simple Makefile that will run the symbiflow counter test on the basys3 board. Highlighted lines within the code below are of particular interest and will change depending on your design and hardware.
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.. code-block:: bash
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:name: makefile-example
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@ -61,16 +61,16 @@ Line 4 in the Makefile shows how to add HDL files to the design. The general syn
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.. code-block:: bash
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:name: multi-file-example
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<HDL language> := ${current_dir}/<HDL file> \
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<HDL language> := ${current_dir}/<HDL file 1> \
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${current_dir}/<HDL file>\
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${current_dir}/<HDL file 2>\
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${current_dir}/<HDL file> \
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${current_dir}/<HDL file 3> \
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${current_dir}/<HDL file> \
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${current_dir}/<HDL file 4> \
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...
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You could also use wildcards to collect all HDL file types of a specific extension and add them to your design. For example, if you wanted to add all verilog files within the current directory to your design you should replace line 4 in the makefile with:
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You could also use wildcards to collect all HDL file types of a specific extension and add them to your design. For example, if you wanted to add all verilog files within the current directory to your design you could replace line 4 in the Makefile with:
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.. code-block:: bash
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:name: wildcard-example
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@ -78,9 +78,13 @@ You could also use wildcards to collect all HDL file types of a specific extensi
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VERILOG := ${current_dir}/*.v
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As of this writing symbiflow only supports Verilog and SystemVerilog HDL.
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To include SystemVerilog in your design simply change the ``*.v`` above to a ``*.sv``. You might also want to change the ``VERILOG`` bash variables throughout the Makefile to ``SYSTEM_VERILOG`` to improve readability.
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Setting the device constraints
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.. note::
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As of this writing symbiflow only supports Verilog and SystemVerilog HDL by default.
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Setting the device properties
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------------------------------
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Line 5 in the example sets the device type for the project. Several different board types are supported and a listing of the commands for each board type follows:
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@ -179,7 +183,7 @@ As shown on line 9 of the example makefile you will also need to define the part
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Constraint files
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----------------
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Line 10 shows how you can specify what the constraint files are for your design. The general syntax depends on wether you are using XDC files or a SDC+PCF pair:
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Line 10 shows how you can specify what the constraint files are being used for your design. The general syntax depends on wether you are using XDC files or a SDC+PCF pair:
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.. tabs::
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@ -196,4 +200,60 @@ Line 10 shows how you can specify what the constraint files are for your design.
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PCF := ${current_dir}/<name of PCF file>
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SDC := ${current_dir}/<name of SDC file>
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Note that the lines 22, 25, 28, and 31 (.eblif, net, place, and route) may will need to change depending on if you use an XDC file or some combination of SDC, PCF and XDC.
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Note that the lines 22, 25, 28, and 31 (.eblif, net, place, and route) will also need to change depending on if you use an XDC file or some combination of SDC, PCF and XDC files. The following snippets show the differences and the areas that will need to change:
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.. tabs::
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.. group-tab:: XDC
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.. code-block:: bash
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:emphasize-lines: 2
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${BOARD_BUILDDIR}/${TOP}.eblif: | ${BOARD_BUILDDIR}
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cd ${BOARD_BUILDDIR} && symbiflow_synth -t ${TOP} -v ${VERILOG} -d ${BITSTREAM_DEVICE} -p ${PARTNAME} -x ${XDC} 2>&1 > /dev/null
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${BOARD_BUILDDIR}/${TOP}.net: ${BOARD_BUILDDIR}/${TOP}.eblif
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cd ${BOARD_BUILDDIR} && symbiflow_pack -e ${TOP}.eblif -d ${DEVICE} 2>&1 > /dev/null
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${BOARD_BUILDDIR}/${TOP}.place: ${BOARD_BUILDDIR}/${TOP}.net
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cd ${BOARD_BUILDDIR} && symbiflow_place -e ${TOP}.eblif -d ${DEVICE} -n ${TOP}.net -P ${PARTNAME} 2>&1 > /dev/null
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${BOARD_BUILDDIR}/${TOP}.route: ${BOARD_BUILDDIR}/${TOP}.place
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cd ${BOARD_BUILDDIR} && symbiflow_route -e ${TOP}.eblif -d ${DEVICE} 2>&1 > /dev/null
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.. group-tab:: SDC+PCF
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.. code-block:: bash
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:emphasize-lines: 5, 8, 11
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${BOARD_BUILDDIR}/${TOP}.eblif: | ${BOARD_BUILDDIR}
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cd ${BOARD_BUILDDIR} && symbiflow_synth -t ${TOP} -v ${VERILOG} -d ${BITSTREAM_DEVICE} -p ${PARTNAME}
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${BOARD_BUILDDIR}/${TOP}.net: ${BOARD_BUILDDIR}/${TOP}.eblif
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cd ${BOARD_BUILDDIR} && symbiflow_pack -e ${TOP}.eblif -d ${DEVICE} -s ${SDC}
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${BOARD_BUILDDIR}/${TOP}.place: ${BOARD_BUILDDIR}/${TOP}.net
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cd ${BOARD_BUILDDIR} && symbiflow_place -e ${TOP}.eblif -d ${DEVICE} -p ${PCF} -n ${TOP}.net -P ${PARTNAME} -s ${SDC} 2>&1 > /dev/null
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${BOARD_BUILDDIR}/${TOP}.route: ${BOARD_BUILDDIR}/${TOP}.place
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cd ${BOARD_BUILDDIR} && symbiflow_route -e ${TOP}.eblif -d ${DEVICE} -s ${SDC} 2>&1 > /dev/null
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.. group-tab:: SDC+PCF+XDC
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.. code-block:: bash
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:emphasize-lines: 2, 5, 8, 11
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${BOARD_BUILDDIR}/${TOP}.eblif: | ${BOARD_BUILDDIR}
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cd ${BOARD_BUILDDIR} && symbiflow_synth -t ${TOP} -v ${VERILOG} -d ${BITSTREAM_DEVICE} -p ${PARTNAME} -x ${XDC} 2>&1 > /dev/null
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${BOARD_BUILDDIR}/${TOP}.net: ${BOARD_BUILDDIR}/${TOP}.eblif
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cd ${BOARD_BUILDDIR} && symbiflow_pack -e ${TOP}.eblif -d ${DEVICE} -s ${SDC} 2>&1 > /dev/null
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${BOARD_BUILDDIR}/${TOP}.place: ${BOARD_BUILDDIR}/${TOP}.net
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cd ${BOARD_BUILDDIR} && symbiflow_place -e ${TOP}.eblif -d ${DEVICE} -p ${PCF} -n ${TOP}.net -P ${PARTNAME} -s ${SDC} 2>&1 > /dev/null
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${BOARD_BUILDDIR}/${TOP}.route: ${BOARD_BUILDDIR}/${TOP}.place
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cd ${BOARD_BUILDDIR} && symbiflow_route -e ${TOP}.eblif -d ${DEVICE} -s ${SDC} 2>&1 > /dev/null
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Lines 33-37 (running ``symbiflow_write_fasm`` and ``symbiflow_write_bitstream``) typically do not change from design to design.
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@ -1,9 +1,9 @@
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Using Symbiflow to upload your own designs
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===========================================
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This section describes how you can upload you're own designs to an FPGA from start to finish using only open source tools.
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This section describes how to upload you're own designs to an FPGA from start to finish using only open source tools.
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Prepareing your environment
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Preparing your environment
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----------------------------
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Before building any example, set the installation directory to match what you
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set it to earlier, for example:
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@ -47,6 +47,9 @@ Finally, enter your working Conda environment:
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conda activate $FPGA_FAM
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.. note::
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You will need to run the commands for preparing your conda environment each time you open a new terminal. You will also need to activate the Conda environment for your hardware before you attempt to build your designs. It might be a good idea to add the above commands to your ``.bashrc`` either as functions or aliases to save yourself some repetitive typing.
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Preparing Your Design
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@ -55,27 +58,25 @@ Building a design in symbiflow requires three simple parts, the HDL files for yo
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HDL files
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++++++++++
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Symbiflow provides support for both Verilog and SystemVerilog HDL code. Use whichever method you prefer and add your design files to the directory of choice. If you are using the provided Makefiles to build your design, your top level module should be declared as ``module top (...``.
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Symbiflow provides support for both Verilog and SystemVerilog HDL code. Use whichever method you prefer and add your design files to the directory of choice. If you are using the provided Makefiles to build your design, your top level module should be declared as ``module top (...``. Failure to do so will result in an error during the build process stating something to the effect of ``ERROR: Module 'top' not found!``
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Constraint file
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++++++++++++++++
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The Symbiflow tool chain supports both .XDC and .PCF+.SDC formats for constraint files. Use whichever method you prefer and add your constraint file(s) to the design directory.
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.. warning::
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In its current state, symbiflow-examples does not provide support for dictionaries within XDC files by default. To support this functionality you will need to use the `XDC-plugin <https://github.com/SymbiFlow/yosys-symbiflow-plugins/tree/master/xdc-plugin>`_ from ``symbiflow-yosys-plugins.`` Failure to install the plugin before attempting to use dictionaries within your XDC file may result in a faulty bitstream.
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Makefile
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+++++++++
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To learn about how the Makefiles in symbiflow work see the `Understanding the Makefile in Symbiflow <Understanding-Makefile.html>`_ page.
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To learn about how Makefiles in symbiflow work, see the `Understanding the Makefile in Symbiflow <Understanding-Makefile.html>`_ page.
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If you have used verilog as your HDL and an XDC as your constraint, you can add this :download:`Makefile <master_makefile/Makefile>` to your design directory instead of building your own.
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Building your personal projects
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-------------------------------
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Before you begin building your design navigate to the directory where you have stored your Makefile, HDL, and constraint files:
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Before you begin building your design, navigate to the directory where you have stored your Makefile, HDL, and constraint files:
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.. code-block:: bash
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:name: your-directory
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@ -98,7 +99,7 @@ Then, depending on your board type run:
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.. code-block:: bash
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:name: example-counter-a100t-group
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TARGET="arty_100" make -C .
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TARGET="arty_100" make -C .
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.. group-tab:: Nexus4
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@ -122,7 +123,7 @@ If your design builds without error, the bitstream can be found in the following
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cd build/<board>
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Finally, for **Arty and Basys3**, you can upload the design with:
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Once you navigate to the directory containing the bitstream, use the following commands on the **Arty and Basys3** to upload the design to your board:
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.. code-block:: bash
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@ -130,16 +131,16 @@ Finally, for **Arty and Basys3**, you can upload the design with:
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.. tip::
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Many of the commands needed to build a project are run many times. You might consider adding a few aliases or even a few bash functions to your .bashrc file to save yourself some typing or repeated copy/paste.
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For example, instead of using the somewhat cumbersome command used to upload the bitstream to arty or basys3 every time, you could just add the following lines to your bashrc file:
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Many of the commands needed to build a project are run multiple times with little to no variation. You might consider adding a few aliases or even a few bash functions to your .bashrc file to save yourself some typing or repeated copy/paste.
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For example, instead of using the somewhat cumbersome command used to upload the bitstream to Xilinx 7 series FPGA every time, you could just add the following lines to your bashrc file:
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.. code-block:: bash
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:name: bash-functions
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symbi_bit() {
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#Creates and downloads the bitstream to Basys 3 or Arty boards:
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openocd -f /home/chem3000/opt/symbiflow/xc7/conda/envs/xc7/share/openocd/scripts/board/digilent_arty.cfg -c "init; pld load 0 top.bit; exit"
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#Creates and downloads the bitstream to Xilinx 7 series FPGA:
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openocd -f <Your install directory>/xc7/conda/envs/xc7/share/openocd/scripts/board/digilent_arty.cfg -c "init; pld load 0 top.bit; exit"
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}
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Now whenever you need to download a bitstream to the arty or basys you can simply type ``symbi_bit`` into the terminal and hit enter.
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Now whenever you need to download a bitstream to the Xilinx-7 series you can simply type ``symbi_bit`` into the terminal and hit enter.
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