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ci: save bitstreams and plots to separated artifacts 

Signed-off-by: Unai Martinez-Corral <umartinezcorral@antmicro.com>
This commit is contained in:
Unai Martinez-Corral 2022-05-31 10:28:01 +02:00
parent a3023c65d6
commit fe5f069ee6
1 changed files with 12 additions and 6 deletions
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18
.github/workflows/sphinx-tuttest.yml vendored
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@ -76,9 +76,12 @@ jobs:
- uses: actions/upload-artifact@v3 - uses: actions/upload-artifact@v3
with: with:
name: f4pga-examples-bitstreams name: f4pga-examples-bitstreams
path: | path: '**/*.bit'
**/*.bit
**/plot_*.svg - uses: actions/upload-artifact@v3
with:
name: f4pga-examples-plots
path: '**/plot_*.svg'
Test-Surelog: Test-Surelog:
@ -130,6 +133,9 @@ jobs:
- uses: actions/upload-artifact@v3 - uses: actions/upload-artifact@v3
with: with:
name: f4pga-examples-bitstreams-systemverilog-plugin name: f4pga-examples-bitstreams-systemverilog-plugin
path: | path: '**/*.bit'
**/*.bit
**/plot_*.svg - uses: actions/upload-artifact@v3
with:
name: f4pga-examples-plots-systemverilog-plugin
path: '**/plot_*.svg'