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Merge pull request #142 from cjearls/addingNexys4DDRtoCounterTest 

added support for Nexys4DDR board in counter_test
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Karol Gugala 2021-04-27 10:03:38 +02:00 committed by GitHub
parent 9a114c44c0 d2b0747fbe
commit ffebb33ee0
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GPG Key ID: 4AEE18F83AFDEB23
4 changed files with 27 additions and 0 deletions
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1
docs/collect_readmes.py
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@ -5,6 +5,7 @@ from docutils.core import publish_doctree
full_name_lut = { full_name_lut = {
'a35t': 'Arty 35T', 'a35t': 'Arty 35T',
'a100t': 'Arty 100T', 'a100t': 'Arty 100T',
'nexys4ddr': 'Nexys 4 DDR',
'basys3': 'Basys 3', 'basys3': 'Basys 3',
'eos_s3': 'EOS S3', 'eos_s3': 'EOS S3',
'zybo': 'Zybo Z7', 'zybo': 'Zybo Z7',

5
xc7/counter_test/Makefile
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@ -15,6 +15,11 @@ else ifeq ($(TARGET),arty_100)
XDC:=${current_dir}/arty.xdc XDC:=${current_dir}/arty.xdc
DEVICE:= xc7a100t_test DEVICE:= xc7a100t_test
BOARD_BUILDDIR := ${BUILDDIR}/arty_100 BOARD_BUILDDIR := ${BUILDDIR}/arty_100
else ifeq ($(TARGET),nexys4ddr)
PARTNAME:= xc7a100tcsg324-1
XDC:=${current_dir}/nexys4ddr.xdc
DEVICE:= xc7a100t_test
BOARD_BUILDDIR := ${BUILDDIR}/nexys4ddr
else ifeq ($(TARGET),zybo) else ifeq ($(TARGET),zybo)
PARTNAME:= xc7z010clg400-1 PARTNAME:= xc7z010clg400-1
XDC:=${current_dir}/zybo.xdc XDC:=${current_dir}/zybo.xdc

5
xc7/counter_test/README.rst
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@ -16,6 +16,11 @@ counter example, depending on your hardware, run:
TARGET="arty_100" make -C counter_test TARGET="arty_100" make -C counter_test
.. code-block:: bash
:name: example-counter-nexys4ddr-group
TARGET="nexys4ddr" make -C counter_test
.. code-block:: bash .. code-block:: bash
:name: example-counter-basys3-group :name: example-counter-basys3-group

16
xc7/counter_test/nexys4ddr.xdc Normal file
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@ -0,0 +1,16 @@
# Clock pin
set_property PACKAGE_PIN E3 [get_ports {clk}]
set_property IOSTANDARD LVCMOS33 [get_ports {clk}]
# LEDs
set_property PACKAGE_PIN H17 [get_ports {led[0]}]
set_property PACKAGE_PIN K15 [get_ports {led[1]}]
set_property PACKAGE_PIN J13 [get_ports {led[2]}]
set_property PACKAGE_PIN N14 [get_ports {led[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[3]}]
# Clock constraints
create_clock -period 10.0 [get_ports {clk}]