Merge pull request #142 from cjearls/addingNexys4DDRtoCounterTest

added support for Nexys4DDR board in counter_test

docs/collect_readmes.py

@@ -5,6 +5,7 @@ from docutils.core import publish_doctree
 full_name_lut = {
     'a35t': 'Arty 35T',
     'a100t': 'Arty 100T',
+    'nexys4ddr': 'Nexys 4 DDR',
     'basys3': 'Basys 3',
     'eos_s3': 'EOS S3',
     'zybo': 'Zybo Z7',

xc7/counter_test/Makefile

@@ -15,6 +15,11 @@ else ifeq ($(TARGET),arty_100)
   XDC:=${current_dir}/arty.xdc
   DEVICE:= xc7a100t_test
   BOARD_BUILDDIR := ${BUILDDIR}/arty_100
+else ifeq ($(TARGET),nexys4ddr)
+  PARTNAME:= xc7a100tcsg324-1
+  XDC:=${current_dir}/nexys4ddr.xdc
+  DEVICE:= xc7a100t_test
+  BOARD_BUILDDIR := ${BUILDDIR}/nexys4ddr
 else ifeq ($(TARGET),zybo)
   PARTNAME:= xc7z010clg400-1
   XDC:=${current_dir}/zybo.xdc

xc7/counter_test/README.rst

@@ -16,6 +16,11 @@ counter example, depending on your hardware, run:
    TARGET="arty_100" make -C counter_test
 
 
+.. code-block:: bash
+   :name: example-counter-nexys4ddr-group
+
+   TARGET="nexys4ddr" make -C counter_test
+
 .. code-block:: bash
    :name: example-counter-basys3-group
 

xc7/counter_test/nexys4ddr.xdc

@@ -0,0 +1,16 @@
+# Clock pin
+set_property PACKAGE_PIN E3 [get_ports {clk}]
+set_property IOSTANDARD LVCMOS33 [get_ports {clk}]
+
+# LEDs
+set_property PACKAGE_PIN H17  [get_ports {led[0]}]
+set_property PACKAGE_PIN K15  [get_ports {led[1]}]
+set_property PACKAGE_PIN J13  [get_ports {led[2]}]
+set_property PACKAGE_PIN N14  [get_ports {led[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {led[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {led[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {led[3]}]
+
+# Clock constraints
+create_clock -period 10.0 [get_ports {clk}]