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14 lines
394 B
Systemverilog
14 lines
394 B
Systemverilog
`timescale 1ns / 1ps
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`default_nettype none
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module top(
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input wire logic clk, btnc, sw,
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output logic[3:0] anode,
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output logic[7:0] segment
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);
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logic[15:0] digitData;
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stopwatch SW0(clk, btnc, sw, digitData[3:0], digitData[7:4], digitData[11:8], digitData[15:12]);
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SevenSegmentControl SSC0(clk, btnc, digitData, 4'b1111 , 4'b0100 , anode, segment);
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endmodule
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