f4pga-examples/eos-s3/btn_counter
Paweł Czarnecki 40016790ef eos-s3: btn_counter: use F4PGA build flow by default
Signed-off-by: Paweł Czarnecki <pczarnecki@antmicro.com>
2022-08-01 17:54:29 +02:00
..
Makefile eos-s3: btn_counter: use F4PGA build flow by default 2022-08-01 17:54:29 +02:00
README.rst eos-s3: btn_counter: set FPGA_FAM one more time before make 2022-06-22 13:02:56 +02:00
btn_counter.v formatted files 2021-05-13 12:07:40 -06:00
chandalar.pcf eos-s3: btn_counter: fix pcf after bumping VPR 2022-06-07 15:02:34 +02:00
dummy.sdc eos-s3/environment: update 2022-07-31 20:10:02 +02:00
flow.json eos-s3: btn_counter: use F4PGA build flow by default 2022-08-01 17:54:29 +02:00

README.rst

Button counter
~~~~~~~~~~~~~~

This example design features a simple 4-bit counter driving LEDs. To build the
counter example, run the following command:

.. code-block:: bash
   :name: eos-s3-counter

   #FIXME: make sure FPGA_FAM is available and remove env var export
   export FPGA_FAM=eos-s3
   make -C btn_counter