f4pga-examples/eos-s3/btn_counter
Unai Martinez-Corral 4cfab2ee93 eos-s3/btn_counter/Makefile: add missing jlink dump
Signed-off-by: Unai Martinez-Corral <umartinezcorral@antmicro.com>
2022-08-04 07:29:46 +02:00
..
Makefile eos-s3/btn_counter/Makefile: add missing jlink dump 2022-08-04 07:29:46 +02:00
README.rst docs/building-examples: export FPGA_FAM 2022-08-02 11:57:04 +02:00
btn_counter.v
chandalar.pcf
dummy.sdc
flow.json eos-s3: btn_counter: use F4PGA build flow by default 2022-08-01 17:54:29 +02:00

README.rst

Button counter
~~~~~~~~~~~~~~

This example design features a simple 4-bit counter driving LEDs. To build the
counter example, run the following command:

.. code-block:: bash
   :name: eos-s3-counter

   make -C btn_counter