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https://github.com/chipsalliance/f4pga-examples.git
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7b623cdfdf
Signed-off-by: Tim 'mithro' Ansell <me@mith.ro>
11 lines
188 B
Text
11 lines
188 B
Text
# basys3 100 MHz CLK
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set_io clk W5
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set_io tx A18
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set_io rx B18
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# out[0:15] correspond with LD0-LD15 on the basys3
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set_io led[0] U16
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set_io led[1] E19
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set_io led[2] U19
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set_io led[3] V19
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