f4pga-examples/xc7/litex_sata_demo
Alessandro Comodi e18e544825 xc7: add lite SATA example
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2021-11-30 13:40:41 +01:00
..
Makefile xc7: add lite SATA example 2021-11-30 13:40:41 +01:00
README.rst xc7: add lite SATA example 2021-11-30 13:40:41 +01:00
VexRiscv.v xc7: add lite SATA example 2021-11-30 13:40:41 +01:00
litesata.v xc7: add lite SATA example 2021-11-30 13:40:41 +01:00
mem.init xc7: add lite SATA example 2021-11-30 13:40:41 +01:00
mem_1.init xc7: add lite SATA example 2021-11-30 13:40:41 +01:00
mem_2.init xc7: add lite SATA example 2021-11-30 13:40:41 +01:00
nexys_video.xdc xc7: add lite SATA example 2021-11-30 13:40:41 +01:00

README.rst

LiteX SATA demo
~~~~~~~~~~~~~~~

This example design features a Litex SoC based around VexRiscv soft
CPU. It also includes a DDR controller and a SATA core . To build the litex SATA example,
run the following commands:

To build the litex SATA demo example, first re-navigate to the directory that contains examples for Xilinx 7-Series FPGAs. Then depending on your hardware, run:


.. code-block:: bash
   :name: example-litex-sata-nexys-video-group

   TARGET="nexys_video" make -C litex_sata_demo

At completion, the bitstreams are located in the build directory:

.. code-block:: bash

   litex_sata_demo/build/<board>