55 lines
1.1 KiB
Systemverilog
55 lines
1.1 KiB
Systemverilog
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module top(
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input wire logic clk,
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input wire logic btnu,
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input wire logic [7:0] sw,
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input wire logic btnc,
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output logic [3:0] anode,
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output logic [7:0] segment,
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output logic tx_out,
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output logic tx_debug);
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logic reset;
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assign reset = btnu;
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assign tx_debug = tx_out;
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logic btnc_r;
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logic btnc_r2;
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logic send_character;
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always_ff@(posedge clk)
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begin
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btnc_r <= btnc;
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btnc_r2 <= btnc_r;
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end
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debounce debounce_inst(
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.clk(clk),
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.reset(reset),
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.noisy(btnc_r2),
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.debounced(send_character)
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);
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tx tx_inst(
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.clk (clk),
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.Reset (reset),
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.Send (send_character),
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.Din (sw),
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.Sent (),
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.Sout (tx_out)
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);
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SevenSegmentControl SSC (
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.clk(clk),
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.reset(reset),
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.dataIn({8'h00, sw}),
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.digitDisplay(4'h3),
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.digitPoint(4'h0),
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.anode(anode),
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.segment(segment)
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);
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endmodule
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