f4pga-examples/xc7/timer
Karol Gugala f0c5adcb75 Raname to F4PGA
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
2022-02-18 18:15:44 +01:00
..
Makefile fixed documentation and makefiles. Renamed common makefile. 2021-11-11 13:47:47 -07:00
README.rst Raname to F4PGA 2022-02-18 18:15:44 +01:00
basys3.xdc rebased onto main 2021-08-20 14:05:28 -06:00
clock.sv fixed module parameters to conform to conventions 2021-08-20 13:11:11 -06:00
display_control.sv Ran PWM and timer through verible formatter and linter 2021-08-20 13:11:11 -06:00
modify_count.sv Ran PWM and timer through verible formatter and linter 2021-08-20 13:11:11 -06:00
time_counter.sv Ran PWM and timer through verible formatter and linter 2021-08-20 13:11:11 -06:00
timer.sv fixed module parameters to conform to conventions 2021-08-20 13:11:11 -06:00

README.rst

Timer
~~~~~~

This example is built specifically for the basys3 and demonstrates a greater variety of I/O 
then previous designs. It also demonstrates F4PGA's support for code written in System Verilog 
as well as its support of dictionaries in XDCs. To build this example run the following commands:

.. code-block:: bash
   :name: example-watch-basys3

   make -C timer


At completion, the bitstream is located in the build directory:

.. code-block:: bash

   timer/build/basys3

Now, you can upload the design with:

.. code-block:: bash

   TARGET="basys3" make download -C timer

After downloading the bitstream you can start and stop the watch by toggling switch 0 on the board.
Press the center button to reset the counter. The following gives a visual example:

.. image:: ../../docs/images/timer.gif
   :align: center
   :width: 50%