f4pga-examples/xc7/linux_litex_demo/Makefile

11 lines
300 B
Makefile

current_dir := ${CURDIR}
TOP := top
SOURCES := ${current_dir}/baselitex_arty.v \
${current_dir}/../../third_party/vexriscv-verilog/VexRiscv_Linux.v
PCF := ${current_dir}/arty.pcf
SDC := ${current_dir}/arty.sdc
XDC := ${current_dir}/arty.xdc
include ${current_dir}/../../common/common.mk