33 lines
1.2 KiB
Plaintext
33 lines
1.2 KiB
Plaintext
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# Copyright (C) 2020-2022 F4PGA Authors.
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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#
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# https://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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#
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# SPDX-License-Identifier: Apache-2.0
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# Clock pin
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set_property PACKAGE_PIN E3 [get_ports {CLK}]
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set_property IOSTANDARD LVCMOS33 [get_ports {CLK}]
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# LEDs
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set_property PACKAGE_PIN H5 [get_ports {LEDs[0]}]
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set_property PACKAGE_PIN J5 [get_ports {LEDs[1]}]
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set_property PACKAGE_PIN T9 [get_ports {LEDs[2]}]
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set_property PACKAGE_PIN T10 [get_ports {LEDs[3]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {LEDs[0]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {LEDs[1]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {LEDs[2]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {LEDs[3]}]
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# Clock constraints
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create_clock -period 10.0 [get_ports {CLK}]
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