docs/status: content moved from website index
Signed-off-by: Unai Martinez-Corral <umartinezcorral@antmicro.com>
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Unai Martinez-Corral
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32
docs/conf.py
32
docs/conf.py
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@ -6,9 +6,33 @@
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import sys, os
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from pathlib import Path
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from tabulate import tabulate
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ROOT = Path(__file__).resolve().parent
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#sys.path.insert(0, os.path.abspath('.'))
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# -- General configuration -----------------------------------------------------
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# -- Generate status.inc -----------------------------------------------------------------------------------------------
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with (ROOT / "status.inc").open("w", encoding="utf-8") as wfptr:
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wfptr.write(
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tabulate(
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[
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["[Basic Tiles] Logic", "Yes", "Yes", "Yes", "Yes"],
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["[Basic Tiles] Block RAM", "Yes", "Yes", "Partial", "Yes"],
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["[Advanced Tiles] DSP", "Yes", "Yes", "Partial", "Yes"],
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["[Advanced Tiles] Hard Blocks", "Yes", "Yes", "Partial", "Yes"],
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["[Advanced Tiles] Clock Tiles", "Yes", "Yes", "Yes", "Yes"],
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["[Advanced Tiles] IO Tiles", "Yes", "Yes", "Yes", "Yes"],
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["[Routing] Logic", "Yes", "Yes", "Yes", "Yes"],
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["[Routing] Clock", "Yes", "Yes", "Yes", "Yes"],
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],
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headers=["", "Project Icestorm", "Project Trellis ", "Project X-Ray", "QuickLogic Database"],
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tablefmt="rst",
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)
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)
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# -- General configuration ---------------------------------------------------------------------------------------------
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project = 'F4PGA'
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basic_filename = 'f4pga-docs'
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@ -47,7 +71,7 @@ rst_prolog = """
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:format: html
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"""
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# -- Options for HTML output ---------------------------------------------------
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# -- Options for HTML output -------------------------------------------------------------------------------------------
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html_show_sourcelink = True
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@ -66,7 +90,7 @@ html_static_path = ['_static']
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html_logo = str(Path(html_static_path[0]) / 'logo.svg')
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html_favicon = str(Path(html_static_path[0]) / 'favicon.svg')
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# -- Options for LaTeX output --------------------------------------------------
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# -- Options for LaTeX output ------------------------------------------------------------------------------------------
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latex_documents = [
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('index', basic_filename+'.tex', project,
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@ -99,7 +123,7 @@ latex_elements = {
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'''
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}
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# -- Options for manual page output --------------------------------------------
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# -- Options for manual page output ------------------------------------------------------------------------------------
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man_pages = [
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('index', basic_filename, project,
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@ -1,3 +1,4 @@
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Sphinx==3.0.4
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http://github.com/SymbiFlow/sphinx_symbiflow_theme/archive/chips.zip#sphinx-symbiflow-theme
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http://github.com/SymbiFlow/sphinx-verilog-domain/archive/master.zip#sphinx-verilog-domain
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tabulate
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@ -1,38 +1,29 @@
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Supported Architectures
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#######################
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* `Xilinx 7-Series <https://www.xilinx.com/video/fpga/7-series-fpga-overview.html>`__:
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the most popular Xilinx FPGA family.
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* `Lattice ice40 <http://www.latticesemi.com/iCE40>`__:
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world's smallest FPGAs for mobile devices.
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* `Lattice ecp5 <https://www.latticesemi.com/Products/FPGAandCPLD/ECP5>`__:
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low cost FPGAs with high performance features.
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* `QuickLogic EOS S3 <https://www.quicklogic.com/products/eos-s3/>`__:
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FPGA + CPU sensor processing platform.
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* `QuickLogic QLF K4N8 <https://www.quicklogic.com/products/efpga/efpga-ip-software/>`__:
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a 24x24 eFPGA with 6144 flip-flops, 4608 LUT4s, adder and shift-register support.
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* Do you want to add more? :ref:`Help us! <Contributing>`
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Bitstream documentation
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=======================
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.. table::
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:align: center
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:widths: 40 20 20 20
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+-----------------+----------+----------+---------+
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| Projects | IceStorm | X-Ray | Trellis |
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+=================+==========+==========+=========+
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| **Basic Tiles** |
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+-----------------+----------+----------+---------+
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| Logic | Yes | Yes | Yes |
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+-----------------+----------+----------+---------+
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| Block RAM | Yes | Partial | N/A |
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+-----------------+----------+----------+---------+
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| **Advanced Tiles** |
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+-----------------+----------+----------+---------+
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| DSP | Yes | No | Yes |
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+-----------------+----------+----------+---------+
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| Hard Blocks | Yes | No | Yes |
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+-----------------+----------+----------+---------+
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| Clock Tiles | Yes | Partial | Yes |
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+-----------------+----------+----------+---------+
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| IO Tiles | Yes | Partial | Yes |
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+-----------------+----------+----------+---------+
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| **Routing** |
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+-----------------+----------+----------+---------+
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| Logic | Yes | Yes | Yes |
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+-----------------+----------+----------+---------+
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| Clock | Yes | Partial | Yes |
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+-----------------+----------+----------+---------+
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.. include:: status.inc
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Boards
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======
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