docs/status: content moved from website index
Signed-off-by: Unai Martinez-Corral <umartinezcorral@antmicro.com>
This commit is contained in:
parent
9bd7e124a3
commit
0ace1e7ef1
32
docs/conf.py
32
docs/conf.py
|
@ -6,9 +6,33 @@
|
||||||
import sys, os
|
import sys, os
|
||||||
from pathlib import Path
|
from pathlib import Path
|
||||||
|
|
||||||
|
from tabulate import tabulate
|
||||||
|
|
||||||
|
ROOT = Path(__file__).resolve().parent
|
||||||
|
|
||||||
#sys.path.insert(0, os.path.abspath('.'))
|
#sys.path.insert(0, os.path.abspath('.'))
|
||||||
|
|
||||||
# -- General configuration -----------------------------------------------------
|
# -- Generate status.inc -----------------------------------------------------------------------------------------------
|
||||||
|
|
||||||
|
with (ROOT / "status.inc").open("w", encoding="utf-8") as wfptr:
|
||||||
|
wfptr.write(
|
||||||
|
tabulate(
|
||||||
|
[
|
||||||
|
["[Basic Tiles] Logic", "Yes", "Yes", "Yes", "Yes"],
|
||||||
|
["[Basic Tiles] Block RAM", "Yes", "Yes", "Partial", "Yes"],
|
||||||
|
["[Advanced Tiles] DSP", "Yes", "Yes", "Partial", "Yes"],
|
||||||
|
["[Advanced Tiles] Hard Blocks", "Yes", "Yes", "Partial", "Yes"],
|
||||||
|
["[Advanced Tiles] Clock Tiles", "Yes", "Yes", "Yes", "Yes"],
|
||||||
|
["[Advanced Tiles] IO Tiles", "Yes", "Yes", "Yes", "Yes"],
|
||||||
|
["[Routing] Logic", "Yes", "Yes", "Yes", "Yes"],
|
||||||
|
["[Routing] Clock", "Yes", "Yes", "Yes", "Yes"],
|
||||||
|
],
|
||||||
|
headers=["", "Project Icestorm", "Project Trellis ", "Project X-Ray", "QuickLogic Database"],
|
||||||
|
tablefmt="rst",
|
||||||
|
)
|
||||||
|
)
|
||||||
|
|
||||||
|
# -- General configuration ---------------------------------------------------------------------------------------------
|
||||||
|
|
||||||
project = 'F4PGA'
|
project = 'F4PGA'
|
||||||
basic_filename = 'f4pga-docs'
|
basic_filename = 'f4pga-docs'
|
||||||
|
@ -47,7 +71,7 @@ rst_prolog = """
|
||||||
:format: html
|
:format: html
|
||||||
"""
|
"""
|
||||||
|
|
||||||
# -- Options for HTML output ---------------------------------------------------
|
# -- Options for HTML output -------------------------------------------------------------------------------------------
|
||||||
|
|
||||||
html_show_sourcelink = True
|
html_show_sourcelink = True
|
||||||
|
|
||||||
|
@ -66,7 +90,7 @@ html_static_path = ['_static']
|
||||||
html_logo = str(Path(html_static_path[0]) / 'logo.svg')
|
html_logo = str(Path(html_static_path[0]) / 'logo.svg')
|
||||||
html_favicon = str(Path(html_static_path[0]) / 'favicon.svg')
|
html_favicon = str(Path(html_static_path[0]) / 'favicon.svg')
|
||||||
|
|
||||||
# -- Options for LaTeX output --------------------------------------------------
|
# -- Options for LaTeX output ------------------------------------------------------------------------------------------
|
||||||
|
|
||||||
latex_documents = [
|
latex_documents = [
|
||||||
('index', basic_filename+'.tex', project,
|
('index', basic_filename+'.tex', project,
|
||||||
|
@ -99,7 +123,7 @@ latex_elements = {
|
||||||
'''
|
'''
|
||||||
}
|
}
|
||||||
|
|
||||||
# -- Options for manual page output --------------------------------------------
|
# -- Options for manual page output ------------------------------------------------------------------------------------
|
||||||
|
|
||||||
man_pages = [
|
man_pages = [
|
||||||
('index', basic_filename, project,
|
('index', basic_filename, project,
|
||||||
|
|
|
@ -1,3 +1,4 @@
|
||||||
Sphinx==3.0.4
|
Sphinx==3.0.4
|
||||||
http://github.com/SymbiFlow/sphinx_symbiflow_theme/archive/chips.zip#sphinx-symbiflow-theme
|
http://github.com/SymbiFlow/sphinx_symbiflow_theme/archive/chips.zip#sphinx-symbiflow-theme
|
||||||
http://github.com/SymbiFlow/sphinx-verilog-domain/archive/master.zip#sphinx-verilog-domain
|
http://github.com/SymbiFlow/sphinx-verilog-domain/archive/master.zip#sphinx-verilog-domain
|
||||||
|
tabulate
|
||||||
|
|
|
@ -1,38 +1,29 @@
|
||||||
Supported Architectures
|
Supported Architectures
|
||||||
#######################
|
#######################
|
||||||
|
|
||||||
|
|
||||||
|
* `Xilinx 7-Series <https://www.xilinx.com/video/fpga/7-series-fpga-overview.html>`__:
|
||||||
|
the most popular Xilinx FPGA family.
|
||||||
|
|
||||||
|
* `Lattice ice40 <http://www.latticesemi.com/iCE40>`__:
|
||||||
|
world's smallest FPGAs for mobile devices.
|
||||||
|
|
||||||
|
* `Lattice ecp5 <https://www.latticesemi.com/Products/FPGAandCPLD/ECP5>`__:
|
||||||
|
low cost FPGAs with high performance features.
|
||||||
|
|
||||||
|
* `QuickLogic EOS S3 <https://www.quicklogic.com/products/eos-s3/>`__:
|
||||||
|
FPGA + CPU sensor processing platform.
|
||||||
|
|
||||||
|
* `QuickLogic QLF K4N8 <https://www.quicklogic.com/products/efpga/efpga-ip-software/>`__:
|
||||||
|
a 24x24 eFPGA with 6144 flip-flops, 4608 LUT4s, adder and shift-register support.
|
||||||
|
|
||||||
|
* Do you want to add more? :ref:`Help us! <Contributing>`
|
||||||
|
|
||||||
|
|
||||||
Bitstream documentation
|
Bitstream documentation
|
||||||
=======================
|
=======================
|
||||||
|
|
||||||
.. table::
|
.. include:: status.inc
|
||||||
:align: center
|
|
||||||
:widths: 40 20 20 20
|
|
||||||
|
|
||||||
+-----------------+----------+----------+---------+
|
|
||||||
| Projects | IceStorm | X-Ray | Trellis |
|
|
||||||
+=================+==========+==========+=========+
|
|
||||||
| **Basic Tiles** |
|
|
||||||
+-----------------+----------+----------+---------+
|
|
||||||
| Logic | Yes | Yes | Yes |
|
|
||||||
+-----------------+----------+----------+---------+
|
|
||||||
| Block RAM | Yes | Partial | N/A |
|
|
||||||
+-----------------+----------+----------+---------+
|
|
||||||
| **Advanced Tiles** |
|
|
||||||
+-----------------+----------+----------+---------+
|
|
||||||
| DSP | Yes | No | Yes |
|
|
||||||
+-----------------+----------+----------+---------+
|
|
||||||
| Hard Blocks | Yes | No | Yes |
|
|
||||||
+-----------------+----------+----------+---------+
|
|
||||||
| Clock Tiles | Yes | Partial | Yes |
|
|
||||||
+-----------------+----------+----------+---------+
|
|
||||||
| IO Tiles | Yes | Partial | Yes |
|
|
||||||
+-----------------+----------+----------+---------+
|
|
||||||
| **Routing** |
|
|
||||||
+-----------------+----------+----------+---------+
|
|
||||||
| Logic | Yes | Yes | Yes |
|
|
||||||
+-----------------+----------+----------+---------+
|
|
||||||
| Clock | Yes | Partial | Yes |
|
|
||||||
+-----------------+----------+----------+---------+
|
|
||||||
|
|
||||||
Boards
|
Boards
|
||||||
======
|
======
|
||||||
|
|
Loading…
Reference in New Issue