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f4pga/common_modules: let VprArgs accept cwd of type Path 

Signed-off-by: Unai Martinez-Corral <umartinezcorral@antmicro.com>
This commit is contained in:
Unai Martinez-Corral 2022-08-16 19:55:26 +02:00
parent f4a85507a3
commit 0d451747ad
5 changed files with 10 additions and 10 deletions
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2
f4pga/common.py
View File

@ -188,7 +188,7 @@ def vpr(mode: str, vprargs: VprArgs, cwd=None):
'--read_rr_graph', vprargs.rr_graph, '--read_rr_graph', vprargs.rr_graph,
'--read_router_lookahead', vprargs.lookahead, '--read_router_lookahead', vprargs.lookahead,
'--read_placement_delay_lookup', vprargs.place_delay '--read_placement_delay_lookup', vprargs.place_delay
] + modeargs + vprargs.optional), cwd=cwd) ] + modeargs + vprargs.optional), cwd=str(cwd))

2
f4pga/common_modules/analysis.py
View File

@ -39,7 +39,7 @@ class analysisModule(Module):
} }
def execute(self, ctx: ModuleContext): def execute(self, ctx: ModuleContext):
build_dir = str(Path(ctx.takes.eblif).parent) build_dir = Path(ctx.takes.eblif).parent
vpr_options = options_dict_to_list(ctx.values.vpr_options) if ctx.values.vpr_options else [] vpr_options = options_dict_to_list(ctx.values.vpr_options) if ctx.values.vpr_options else []

2
f4pga/common_modules/pack.py
View File

@ -50,7 +50,7 @@ class PackModule(Module):
ctx.values, ctx.values,
sdc_file=ctx.takes.sdc sdc_file=ctx.takes.sdc
), ),
cwd=str(build_dir) cwd=build_dir
) )
og_log = build_dir / 'vpr_stdout.log' og_log = build_dir / 'vpr_stdout.log'

4
f4pga/common_modules/place.py
View File

@ -65,7 +65,7 @@ class PlaceModule(Module):
sdc_file=ctx.takes.sdc, sdc_file=ctx.takes.sdc,
vpr_extra_opts=['--fix_clusters', place_constraints] vpr_extra_opts=['--fix_clusters', place_constraints]
), ),
cwd=str(build_dir) cwd=build_dir
) )
# VPR names output on its own. If user requested another name, the # VPR names output on its own. If user requested another name, the
@ -79,7 +79,7 @@ class PlaceModule(Module):
Path(default_output_name(str(place_constraints))).rename(ctx.outputs.place) Path(default_output_name(str(place_constraints))).rename(ctx.outputs.place)
yield 'Saving log...' yield 'Saving log...'
save_vpr_log('place.log', build_dir=str(build_dir)) save_vpr_log('place.log', build_dir=build_dir)
def __init__(self, _): def __init__(self, _):
self.name = 'place' self.name = 'place'

4
f4pga/common_modules/route.py
View File

@ -47,14 +47,14 @@ class RouteModule(Module):
ctx.values, ctx.values,
sdc_file=ctx.takes.sdc sdc_file=ctx.takes.sdc
), ),
cwd=str(build_dir) cwd=build_dir
) )
if ctx.is_output_explicit('route'): if ctx.is_output_explicit('route'):
route_place_file(ctx).rename(ctx.outputs.route) route_place_file(ctx).rename(ctx.outputs.route)
yield 'Saving log...' yield 'Saving log...'
save_vpr_log('route.log', build_dir=str(build_dir)) save_vpr_log('route.log', build_dir=build_dir)
def __init__(self, _): def __init__(self, _):
self.name = 'route' self.name = 'route'