f4pga/common_modules: let VprArgs accept cwd of type Path
Signed-off-by: Unai Martinez-Corral <umartinezcorral@antmicro.com>
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f4a85507a3
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@ -188,7 +188,7 @@ def vpr(mode: str, vprargs: VprArgs, cwd=None):
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'--read_rr_graph', vprargs.rr_graph,
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'--read_router_lookahead', vprargs.lookahead,
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'--read_placement_delay_lookup', vprargs.place_delay
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] + modeargs + vprargs.optional), cwd=cwd)
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] + modeargs + vprargs.optional), cwd=str(cwd))
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@ -39,7 +39,7 @@ class analysisModule(Module):
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}
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def execute(self, ctx: ModuleContext):
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build_dir = str(Path(ctx.takes.eblif).parent)
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build_dir = Path(ctx.takes.eblif).parent
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vpr_options = options_dict_to_list(ctx.values.vpr_options) if ctx.values.vpr_options else []
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@ -50,7 +50,7 @@ class PackModule(Module):
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ctx.values,
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sdc_file=ctx.takes.sdc
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),
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cwd=str(build_dir)
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cwd=build_dir
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)
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og_log = build_dir / 'vpr_stdout.log'
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@ -65,7 +65,7 @@ class PlaceModule(Module):
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sdc_file=ctx.takes.sdc,
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vpr_extra_opts=['--fix_clusters', place_constraints]
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),
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cwd=str(build_dir)
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cwd=build_dir
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)
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# VPR names output on its own. If user requested another name, the
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@ -79,7 +79,7 @@ class PlaceModule(Module):
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Path(default_output_name(str(place_constraints))).rename(ctx.outputs.place)
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yield 'Saving log...'
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save_vpr_log('place.log', build_dir=str(build_dir))
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save_vpr_log('place.log', build_dir=build_dir)
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def __init__(self, _):
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self.name = 'place'
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@ -47,14 +47,14 @@ class RouteModule(Module):
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ctx.values,
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sdc_file=ctx.takes.sdc
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),
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cwd=str(build_dir)
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cwd=build_dir
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)
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if ctx.is_output_explicit('route'):
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route_place_file(ctx).rename(ctx.outputs.route)
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yield 'Saving log...'
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save_vpr_log('route.log', build_dir=str(build_dir))
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save_vpr_log('route.log', build_dir=build_dir)
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def __init__(self, _):
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self.name = 'route'
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