f4pga/flows/common_modules/synth: always use 'read_verilog' (#634)

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Unai Martinez-Corral 2022-09-07 03:55:03 +02:00 committed by GitHub
commit 4170bc49ac
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1 changed files with 12 additions and 12 deletions

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@ -53,17 +53,6 @@ class SynthModule(Module):
def execute(self, ctx: ModuleContext):
yield f"Synthesizing sources{f': {ctx.takes.sources}...' if get_verbosity_level() >= 2 else f'...'}"
tcl = f"tcl {str(get_tcl_wrapper_path())}"
verilog_files = []
# Use append read_verilog commands to the scripts for more sophisticated
# input if arguments are specified. Omit direct input throught `yosys` command.
if ctx.values.read_verilog_args:
args_str = " ".join(ctx.values.read_verilog_args)
for vfile in ctx.takes.sources:
tcl = f"read_verilog {args_str} {vfile}; {tcl}"
else:
verilog_files = ctx.takes.sources
# Set up environment for TCL weirdness
env = environ.copy()
env.update(
@ -79,8 +68,19 @@ class SynthModule(Module):
)
# Execute YOSYS command
args_str = "" if ctx.values.read_verilog_args is None else " ".join(ctx.values.read_verilog_args)
common_sub(
*(["yosys", "-p", tcl] + (["-l", ctx.outputs.synth_log] if ctx.outputs.synth_log else []) + verilog_files),
*(
[
"yosys",
"-p",
(
" ".join([f"read_verilog {args_str} {vfile};" for vfile in ctx.takes.sources])
+ f" tcl {str(get_tcl_wrapper_path())}"
),
]
+ (["-l", ctx.outputs.synth_log] if ctx.outputs.synth_log else [])
),
env=env,
)