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docs/f4pga: update
Signed-off-by: Unai Martinez-Corral <umartinezcorral@antmicro.com>
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Unai Martinez-Corral
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4 changed files with 56 additions and 63 deletions
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@ -5,7 +5,8 @@ Understanding the (deprecated) flow
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.. IMPORTANT::
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This section describes the usage of the now deprecated ``symbiflow_*`` entrypoints/wrappers.
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It is provided for backwards compatibility, so that users of the *old* flow can keep using it.
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It is provided for :gh:`backwards compatibility <chipsalliance/fpga-tool-perf/pull/390#issuecomment-1023487178>`, so
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that users of the *old* flow can keep using it.
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However, it is recommended for new users to use the approach explained in :ref:`pyF4PGA`.
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This section provides valuable information on how each of the commands used to compile and build
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@ -1,52 +1,51 @@
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Package capability status
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#########################
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* Architecture support:
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* Supports incremental builds.
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* Xilinx XC7 (**available** in main branch)
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* Supports multiple configurations for a single project.
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* Synthesis tool: yosys
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* Provides a Python interface to ``F4PGA``, however there's no official API at the moment.
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* PnR tool: VPR
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Architectures and flows
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=======================
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* bitstream generation: yes (xcfasm)
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Xilinx XC7
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----------
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* used in f4pga-examples: :gh:`yes <chipsalliance/f4pga-examples/blob/main/xc7/counter_test/flow.json>`
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* Synthesis tool: yosys
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* PnR tool: VPR
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* bitstream generation: yes (xcfasm)
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* used in f4pga-examples: :gh:`yes <chipsalliance/f4pga-examples/blob/main/xc7/counter_test/flow.json>`
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* Quicklogic EOS-S3 (yosys+VPR flow) (**WIP**, see :ghsharp:`577`)
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Quicklogic EOS-S3
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-----------------
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* Synthesis tool: yosys
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* Synthesis tool: yosys
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* PnR tool: VPR
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* bitstream generation: yes (qlfasm)
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* analysis: ?
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* used in f4pga-examples: no
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* PnR tool: VPR
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Lattice ICE40
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-------------
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* bitstream generation: yes (qlfasm)
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.. IMPORTANT::
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**WIP** :ghsharp:`585`
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* analysis: ?
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* Synthesis tool: yosys
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* PnR tool: nextpnr
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* bitstream generation: yes (icepack)
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* used in f4pga-examples: no
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* used in f4pga-examples: no
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Quicklogic k4n8
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---------------
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* Lattice ICE40 (yosys+nextpnr flow) (**WIP**, see :ghsharp:`585`)
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* Synthesis tool: yosys
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* PnR tool: VPR
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* bitstream generation: yes (qlf_fasm)
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* used in f4pga-examples: no
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* Synthesis tool: yosys
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* PnR tool: nextpnr
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* bitstream generation: yes (icepack)
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* used in f4pga-examples: no
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* Quicklogic k4n8 (Unverified, not officially supported. Might work after some tinkering.)
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* Synthesis tool: yosys
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* PnR tool: VPR
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* bitstream generation: yes (qlf_fasm)
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* used in f4pga-examples: no
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* Incremental builds support
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* Support for multiple configurations for a single project
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* Can be used as a python interface to _F4PGA_, however there's no official _API_ at the moment.
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.. NOTE::
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Unverified, not officially supported.
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Might work after some tinkering.
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@ -9,7 +9,10 @@ The scope of Python F4PGA is threefold:
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* Provide a fine-grained *pythonic* interface to the tools and utilities available as either command-line interfaces
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(CLIs) or application proggraming interfaces (APIs) (either web or through shared libraries).
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* Provide a CLI entrypoint covering the whole flows for end-users to produce bitstreams from HDL and/or software sources.
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* Provide a unified CLI front-end covering the whole flows for end-users to produce bitstreams from HDL and/or software sources.
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It's meant as a future replacement of the deprecated ``symbiflow_*`` shell scripts.
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* Provide a CLI entrypoint for developers contributing to bitstream documentation and testing (continuous integration).
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.. ATTENTION::
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@ -17,32 +20,14 @@ The scope of Python F4PGA is threefold:
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Therefore, it's still a *pre-alpha* and the codebase, commands and flows are subject to change.
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It is strongly suggested not to rely on Python F4PGA until this note is updated/removed.
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This is the current in-development FPGA-oriented build system that's provided with f4pga.
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This package aims to provide a unified front-end for executing *verilog-to-bitstream* and
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other flows for various FPGA platforms. It's meant as a future replacement of
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``symbiflow_*`` shell scripts.
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It contains *EDA* tool wrappers that provide meta-data about the tools, utilities
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related to tracking files and inspection of data used within the flows, scripts used by
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tools within flows, a dependency resolution algorithm and flow templates for various devices.
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``f4pga`` contains *EDA* tool wrappers that provide meta-data about the tools, utilities related to tracking files and
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inspection of data used within the flows, scripts used by tools within flows, a dependency resolution algorithm and flow
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templates for various devices.
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The basic usage requires creation of a ``flow.json`` file describing the FPGA-oriented project.
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You can take
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:gh:`one from the f4pga-examples repository <chipsalliance/f4pga-examples/blob/main/xc7/counter_test/flow.json>`
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as a reference. Alternatively there's a way to configure a flow with command-line parameters only.
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See, for instance, example :gh:`xc7/counter_test/flow.json ➚ <chipsalliance/f4pga-examples/blob/main/xc7/counter_test/flow.json>`.
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Alternatively the flow can be configured through CLI arguments only.
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Once you have your flow created, run ``f4pga build -f flow.json`` to build a default target.
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With a given flow configuration, run ``f4pga build -f flow.json`` builds the default target.
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To learn more about the package and its usage, visit :doc:`Usage`.
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References
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==========
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* :gh:`chipsalliance/fpga-tool-perf#390@issuecomment-1023487178 <chipsalliance/fpga-tool-perf/pull/390#issuecomment-1023487178>`
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* :ghsharp:`2225`
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* :ghsharp:`2371`
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* :ghsharp:`2455`
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* `F4PGA GSoC 2022 project ideas: Generalization of wrapper scripts for installed F4PGA toolchain and making them OS agnostic <https://github.com/f4pga/ideas/blob/master/gsoc-2022-ideas.md#generalization-of-wrapper-scripts-for-installed-f4pga-toolchain-and-making-them-OS-agnostic>`__
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* :gh:`FuseSoc <olofk/fusesoc>` | :gh:`Edalize <olofk/edalize>`
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* `Electronic Design Automation Abstraction (EDA²) <https://edaa-org.github.io/>`__
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See :doc:`Usage` to learn more about ``f4pga``.
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@ -6,3 +6,11 @@ References
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.. bibliography::
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:notcited:
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:labelprefix: R
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f4pga
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=====
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* :ghsharp:`530`
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* `F4PGA GSoC 2022 project ideas: Generalization of wrapper scripts for installed F4PGA toolchain and making them OS agnostic <https://github.com/f4pga/ideas/blob/master/gsoc-2022-ideas.md#generalization-of-wrapper-scripts-for-installed-f4pga-toolchain-and-making-them-OS-agnostic>`__
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* :gh:`FuseSoc <olofk/fusesoc>` | :gh:`Edalize <olofk/edalize>`
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* `Electronic Design Automation Abstraction (EDA²) <https://edaa-org.github.io/>`__
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