ci: use extra verbose mode for f4pga build (#596)

Signed-off-by: Krzysztof Boronski <kboronski@antmicro.com>
2022-08-01 15:03:33 +02:00 · 2022-08-01 15:03:33 +02:00 · d8d27d3216
parent c342fc6ff1
commit d8d27d3216
1 changed files with 1 additions and 1 deletions
--- a/.github/workflows/Pipeline.yml
+++ b/.github/workflows/Pipeline.yml
@ -116,7 +116,7 @@ jobs:
        run: |
          . ./.github/scripts/activate.sh
          cd f4pga-examples
-          f4pga build --flow ../.github/${{ matrix.fam }}_test.json
+          f4pga -vv build --flow ../.github/${{ matrix.fam }}_test.json

      - name: '📤 Upload artifact: ${{ matrix.fam }} bitstream'
        if: matrix.flow == 'F4PGA'