Merge pull request #545 from antmicro/umarcor/docs/yosys-urls
docs: update yosys and icestorm website URL
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@ -134,7 +134,7 @@ Technology mapping in F4PGA toolchain
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.. _Xilinx 7 Series FPGAs Clocking Resources User Guide: https://www.xilinx.com/support/documentation/user_guides/ug472_7Series_Clocking.pdf#page=38
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.. _Xilinx 7 Series FPGAs Clocking Resources User Guide: https://www.xilinx.com/support/documentation/user_guides/ug472_7Series_Clocking.pdf#page=38
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.. _VTR FPGA Architecture Description: https://docs.verilogtorouting.org/en/latest/arch/
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.. _VTR FPGA Architecture Description: https://docs.verilogtorouting.org/en/latest/arch/
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.. _techmap section in the Yosys Manual: http://www.clifford.at/yosys/files/yosys_manual.pdf#page=153
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.. _techmap section in the Yosys Manual: http://yosyshq.net/yosys/files/yosys_manual.pdf#page=153
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It is important to understand the connection between the synthesis and
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It is important to understand the connection between the synthesis and
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implementation tools used in the F4PGA toolchain. As mentioned before,
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implementation tools used in the F4PGA toolchain. As mentioned before,
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@ -405,8 +405,8 @@ More information
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----------------
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----------------
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Additional information about Yosys can be found on the `Yosys Project Website
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Additional information about Yosys can be found on the `Yosys Project Website
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<http://www.clifford.at/yosys/>`_ , or in `Yosys Manual
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<https://yosyshq.net/yosys/>`_ , or in `Yosys Manual
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<http://www.clifford.at/yosys/files/yosys_manual.pdf>`_. You can also compile
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<http://yosyshq.net/yosys/files/yosys_manual.pdf>`_. You can also compile
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one of the tests described in Getting Started section and watch the log file
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one of the tests described in Getting Started section and watch the log file
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to understand which operations are performed by Yosys.
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to understand which operations are performed by Yosys.
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@ -33,12 +33,12 @@ Thus, F4PGA serves as an umbrella project for several activities.
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The central resources are the so-called FPGA "architecture definitions" (i.e. documentation of how specific FPGAs work
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The central resources are the so-called FPGA "architecture definitions" (i.e. documentation of how specific FPGAs work
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internally) and the "interchange schema" (for logical and physical netlists).
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internally) and the "interchange schema" (for logical and physical netlists).
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Those definitions serve as input to frontend and backend tools, such as
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Those definitions serve as input to frontend and backend tools, such as
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`Yosys ➚ <http://www.clifford.at/yosys/>`__,
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`Yosys ➚ <http://yosyshq.net/yosys/>`__,
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:gh:`nextpnr ➚ <YosysHQ/nextpnr>` and `Verilog to Routing ➚ <https://verilogtorouting.org/>`_.
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:gh:`nextpnr ➚ <YosysHQ/nextpnr>` and `Verilog to Routing ➚ <https://verilogtorouting.org/>`_.
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They are created within separate collaborating projects targeting different FPGAs:
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They are created within separate collaborating projects targeting different FPGAs:
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* :doc:`Project X-Ray ➚ <prjxray:index>` for Xilinx 7-Series
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* :doc:`Project X-Ray ➚ <prjxray:index>` for Xilinx 7-Series
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* `Project IceStorm ➚ <http://www.clifford.at/icestorm/>`__ for Lattice iCE40
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* `Project IceStorm ➚ <http://bygone.clairexen.net/icestorm/>`__ for Lattice iCE40
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* :doc:`Project Trellis ➚ <prjtrellis:index>` for Lattice ECP5 FPGAs
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* :doc:`Project Trellis ➚ <prjtrellis:index>` for Lattice ECP5 FPGAs
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More information can be found at :doc:`F4PGA Architecture Definitions ➚ <arch-defs:index>` and :doc:`FPGA Interchange ➚ <interchange:index>`.
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More information can be found at :doc:`F4PGA Architecture Definitions ➚ <arch-defs:index>` and :doc:`FPGA Interchange ➚ <interchange:index>`.
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@ -55,7 +55,7 @@ To prepare a working bitstream for a particular FPGA chip, the toolchain goes th
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This stage is typically pre-built and installed as assets.
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This stage is typically pre-built and installed as assets.
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However, developers contributing to the bitstream documentation might build it.
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However, developers contributing to the bitstream documentation might build it.
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* Then, logic synthesis is carried out in the `Yosys ➚ <http://www.clifford.at/yosys/>`__ framework, which expresses the
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* Then, logic synthesis is carried out in the `Yosys ➚ <http://yosyshq.net/yosys/>`__ framework, which expresses the
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user-provided hardware description by means of the block and connection types available in the chosen chip.
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user-provided hardware description by means of the block and connection types available in the chosen chip.
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* The next step is implementation.
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* The next step is implementation.
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