conf: add logo and favicon; use '_static'

Signed-off-by: Unai Martinez-Corral <umartinezcorral@antmicro.com>
This commit is contained in:
Unai Martinez-Corral 2022-02-10 03:42:47 +01:00
parent b97ef856e8
commit f092b2fa9e
8 changed files with 76 additions and 3 deletions

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66
source/_static/logo.svg Normal file
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@ -4,6 +4,7 @@
# https://www.sphinx-doc.org/en/master/usage/configuration.html
import sys, os
from pathlib import Path
#sys.path.insert(0, os.path.abspath('.'))
@ -60,6 +61,11 @@ html_theme_options = {
'color_accent': 'blue',
}
html_static_path = ['_static']
html_logo = str(Path(html_static_path[0]) / 'logo.svg')
html_favicon = str(Path(html_static_path[0]) / 'favicon.svg')
# -- Options for LaTeX output --------------------------------------------------
latex_documents = [

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@ -25,7 +25,7 @@ all the necessary components for an end-to-end flow.
This pertains both to ASIC and FPGA workflows, although SymbiFlow focuses
on the latter (some parts of SymbiFlow will also be useful in the former).
.. figure:: images/EDA.svg
.. figure:: _static/images/EDA.svg
Project structure
-----------------
@ -48,7 +48,7 @@ collaborating projects targeting different FPGAs - :doc:`Project X-Ray
<http://www.clifford.at/icestorm/>`_ for Lattice iCE40 and :doc:`Project Trellis
<prjtrellis:index>` for Lattice ECP5 FPGAs.
.. figure:: images/parts.svg
.. figure:: _static/images/parts.svg
Current status of bitstream documentation
-----------------------------------------

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@ -15,7 +15,7 @@ SymbiFlow uses different programs to create the bitstream and is
responsible for their proper integration. The procedure of converting
Verilog file into the bitstream is described in the next sections.
.. figure:: ../images/toolchain-flow.svg
.. figure:: ../_static/images/toolchain-flow.svg
:align: center
Symbiflow Toolchain design flow