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f4pga: use envvar F4PGA_ENV_BIN and F4PGA_ENV_SHARE 

Signed-off-by: Unai Martinez-Corral <umartinezcorral@antmicro.com>
This commit is contained in:
Unai Martinez-Corral 2022-04-21 13:25:25 +02:00
parent 2ee6037e05
commit fbf7a4d131
15 changed files with 22 additions and 22 deletions
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4
.github/workflows/Pipeline.yml vendored
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@ -95,8 +95,8 @@ jobs:
run: |
. ./.github/scripts/activate.sh
f4pga-env bin
f4pga-env share
echo "F4PGA_ENV_BIN=$(f4pga-env bin)" >> "$GITHUB_ENV"
echo "F4PGA_ENV_SHARE=$(f4pga-env share)" >> "$GITHUB_ENV"
- name: '🚧 Test make example'
run: |

4
f4pga/wrappers/sh/quicklogic/analysis.f4pga.sh
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@ -19,7 +19,7 @@
set -e
if [ -z $VPRPATH ]; then
export VPRPATH=$(f4pga-env bin)
export VPRPATH="$F4PGA_ENV_BIN"
export PYTHONPATH=${VPRPATH}/python:${VPRPATH}/python/prjxray:${PYTHONPATH}
fi
@ -32,7 +32,7 @@ run_vpr --analysis --gen_post_synthesis_netlist on --verify_file_digests off
mv vpr_stdout.log analysis.log
python3 $(f4pga-env bin)/python/vpr_fixup_post_synth.py \
python3 "$F4PGA_ENV_BIN"/python/vpr_fixup_post_synth.py \
--vlog-in ${TOP}_post_synthesis.v \
--vlog-out ${TOP}_post_synthesis.v \
--sdf-in ${TOP}_post_synthesis.sdf \

2
f4pga/wrappers/sh/quicklogic/generate_bitstream.f4pga.sh
View File

@ -54,6 +54,6 @@ if [ -z $BIT ]; then
exit 1
fi
DB_ROOT=$(f4pga-env share)/fasm_database/${DEVICE}
DB_ROOT="$F4PGA_ENV_SHARE"/fasm_database/${DEVICE}
`which qlf_fasm` --db-root ${DB_ROOT} --format ${BIT_FORMAT} --assemble $FASM $BIT

4
f4pga/wrappers/sh/quicklogic/generate_constraints.f4pga.sh
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@ -36,14 +36,14 @@ else
DEVICE_1=${DEVICE}
fi
SHARE_DIR_PATH=${SHARE_DIR_PATH:=$(f4pga-env share)}
SHARE_DIR_PATH=${SHARE_DIR_PATH:="$F4PGA_ENV_SHARE"}
PINMAP_XML=`realpath ${SHARE_DIR_PATH}/arch/${DEVICE_1}_${DEVICE_1}/${PINMAPXML}`
PROJECT=$(basename -- "$EBLIF")
IOPLACE_FILE="${PROJECT%.*}_io.place"
python3 $(realpath $(f4pga-env bin)/python/create_ioplace.py) \
python3 $(realpath "$F4PGA_ENV_BIN"/python/create_ioplace.py) \
--pcf $PCF \
--blif $EBLIF \
--pinmap_xml $PINMAP_XML \

4
f4pga/wrappers/sh/quicklogic/generate_libfile.f4pga.sh
View File

@ -31,10 +31,10 @@ else
DEVICE_1=${DEVICE}
fi
ARCH_DIR=$(f4pga-env share)/arch/${DEVICE_1}_${DEVICE_1}
ARCH_DIR="$F4PGA_ENV_SHARE"/arch/${DEVICE_1}_${DEVICE_1}
PINMAP_XML=${ARCH_DIR}/${PINMAPXML}
python3 $(f4pga-env bin)/python/create_lib.py \
python3 "$F4PGA_ENV_BIN"/python/create_lib.py \
-n ${DEV}_0P72_SSM40 \
-m fpga_top \
-c $PART \

2
f4pga/wrappers/sh/quicklogic/pack.f4pga.sh
View File

@ -19,7 +19,7 @@
set -e
if [ -z $VPRPATH ]; then
export VPRPATH=$(f4pga-env bin)
export VPRPATH="$F4PGA_ENV_BIN"
export PYTHONPATH=${VPRPATH}/python:${VPRPATH}/python/prjxray:${PYTHONPATH}
fi

2
f4pga/wrappers/sh/quicklogic/place.f4pga.sh
View File

@ -19,7 +19,7 @@
set -e
if [ -z $VPRPATH ]; then
export VPRPATH=$(f4pga-env bin)
export VPRPATH="$F4PGA_ENV_BIN"
export PYTHONPATH=${VPRPATH}/python:${VPRPATH}/python/prjxray:${PYTHONPATH}
fi

4
f4pga/wrappers/sh/quicklogic/ql.f4pga.sh
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@ -20,7 +20,7 @@ set -e
BUILDDIR=build
source $(f4pga-env bin)/vpr_common
source "$F4PGA_ENV_BIN"/vpr_common
VERSION="v2.0.1"
@ -341,7 +341,7 @@ else
PCF_MAKE="\${current_dir}/build/${TOP}_dummy.pcf"
fi
PROCESS_SDC=$(realpath $(f4pga-env bin)/python/process_sdc_constraints.py)
PROCESS_SDC=$(realpath "$F4PGA_ENV_BIN"/python/process_sdc_constraints.py)
if ! [ -z "$SDC" ]; then
if ! [ -f "$SOURCE"/$SDC ];then
echo "The sdc file: $SDC is missing at: $SOURCE"

4
f4pga/wrappers/sh/quicklogic/repack.f4pga.sh
View File

@ -19,7 +19,7 @@
set -e
if [ -z $VPRPATH ]; then
export VPRPATH=$(f4pga-env bin)
export VPRPATH="$F4PGA_ENV_BIN"
export PYTHONPATH=${VPRPATH}/python:${VPRPATH}/python/prjxray:${PYTHONPATH}
fi
@ -31,7 +31,7 @@ DESIGN=${EBLIF/.eblif/}
[ ! -z "${JSON}" ] && JSON_ARGS="--json-constraints ${JSON}" || JSON_ARGS=
[ ! -z "${PCF_PATH}" ] && PCF_ARGS="--pcf-constraints ${PCF_PATH}" || PCF_ARGS=
python3 $(f4pga-env bin)/python/repacker/repack.py \
python3 "$F4PGA_ENV_BIN"/python/repacker/repack.py \
--vpr-arch ${ARCH_DEF} \
--repacking-rules ${ARCH_DIR}/${DEVICE_1}.repacking_rules.json \
$JSON_ARGS \

2
f4pga/wrappers/sh/quicklogic/route.f4pga.sh
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@ -19,7 +19,7 @@
set -e
if [ -z $VPRPATH ]; then
export VPRPATH=$(f4pga-env bin)
export VPRPATH="$F4PGA_ENV_BIN"
export PYTHONPATH=${VPRPATH}/python:${VPRPATH}/python/prjxray:${PYTHONPATH}
fi

4
f4pga/wrappers/sh/quicklogic/synth.f4pga.sh
View File

@ -18,8 +18,8 @@
set -e
export SHARE_DIR_PATH=${SHARE_DIR_PATH:=$(f4pga-env share)}
VPRPATH=${VPRPATH:=$(f4pga-env bin)}
export SHARE_DIR_PATH=${SHARE_DIR_PATH:="$F4PGA_ENV_SHARE"}
VPRPATH=${VPRPATH:="$F4PGA_ENV_BIN"}
SPLIT_INOUTS=`realpath ${VPRPATH}/python/split_inouts.py`
CONVERT_OPTS=`realpath ${VPRPATH}/python/convert_compile_opts.py`

2
f4pga/wrappers/sh/quicklogic/write_fasm.f4pga.sh
View File

@ -19,7 +19,7 @@
set -e
if [ -z $VPRPATH ]; then
export VPRPATH=$(f4pga-env bin)
export VPRPATH="$F4PGA_ENV_BIN"
export PYTHONPATH=${VPRPATH}/python:${VPRPATH}/python/prjxray:${PYTHONPATH}
fi

2
f4pga/wrappers/sh/xc7/generate_constraints.f4pga.sh
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@ -29,7 +29,7 @@ if [ ! -z $PCF ]; then
PCF_OPTS="--pcf $PCF"
fi
SHARE_DIR_PATH=${SHARE_DIR_PATH:=$(f4pga-env share)}
SHARE_DIR_PATH=${SHARE_DIR_PATH:="$F4PGA_ENV_SHARE"}
PROJECT=$(basename -- "$EBLIF")
IOPLACE_FILE="${PROJECT%.*}.ioplace"

2
f4pga/wrappers/sh/xc7/synth.f4pga.sh
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@ -18,7 +18,7 @@
set -e
export SHARE_DIR_PATH=${SHARE_DIR_PATH:=$(f4pga-env share)}
export SHARE_DIR_PATH="$F4PGA_ENV_SHARE"
export TECHMAP_PATH=${SHARE_DIR_PATH}/techmaps/xc7_vpr/techmap
export UTILS_PATH=${SHARE_DIR_PATH}/scripts

2
f4pga/wrappers/sh/xc7/vpr_common.f4pga.sh
View File

@ -16,7 +16,7 @@
#
# SPDX-License-Identifier: Apache-2.0
SHARE_DIR_PATH=${SHARE_DIR_PATH:=$(f4pga-env share)}
SHARE_DIR_PATH=${SHARE_DIR_PATH:="$F4PGA_ENV_SHARE"}
if [ -z $VPR_OPTIONS ]; then
echo "Using default VPR options."