FOSS Flow For FPGA
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Karol Gugala 58d9d7bf24
Merge pull request #580 from antmicro/fix_fasm_append
Fix FASM append operation in FASM module
2022-06-24 14:31:05 +02:00
.github ci/Pipeline: force usage of the deprecated flow in job(s) 'Deprecated' 2022-06-22 13:42:44 +02:00
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f4pga Fix fasm append operation 2022-06-24 07:14:40 -05:00
test add missing headers 2022-06-02 00:35:06 +02:00
third_party Bump third_party/make-env from `0696632` to `59adb0f` 2021-04-16 05:36:52 +00:00
.gitignore f4pga: cleanup and style 2022-04-26 12:16:38 +02:00
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README.md readme: remove base64 logos from shields 2022-06-14 10:19:48 +02:00
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README.md

FOSS Flows For FPGA (F4PGA) project

'Automerge' workflow status

This is the top-level repository for the F4PGA project, which is a Workgroup under the CHIPS Alliance. The elements of the project include (but are not limited to):

F4PGA Workgroup

The F4PGA Workgroup consists of members from different backgrounds, including FPGA vendors (Xilinx and QuickLogic), industrial users (Google, Antmicro) and academia (University of Toronto), who collaborate to build a more open source and software-driven FPGA ecosystem (IP, tools and workflows) to drive the adoption of FPGAs in existing and new use cases, and eliminate barriers of entry.