50 lines
2.9 KiB
Markdown
50 lines
2.9 KiB
Markdown
# FOSS Flow For FPGA (F4PGA) project
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This is the top-level repository for the [F4PGA](https://f4pga.org/) project, which is a Workgroup under the [CHIPS Alliance](https://chipsalliance.org).
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The elements of the project include (but are not limited to):
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* The F4PGA open source FPGA toolchains for programming FPGAs (formerly known as [SymbiFlow](https://github.com/SymbiFlow)).
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This includes:
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* F4PGA documentation: [f4pga.readthedocs.io](https://f4pga.readthedocs.io) (knowledge base)
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* F4PGA Architecture Definitions: [f4pga.readthedocs.io/projects/arch-defs](https://f4pga.readthedocs.io/projects/arch-defs)
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* F4PGA examples: [f4pga-examples.readthedocs.io](https://f4pga-examples.readthedocs.io)
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* [F4PGA Yosys plugins](https://github.com/chipsalliance/yosys-f4pga-plugins)
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* The FPGA interchange format (an interchange format defined by CHIPS Alliance to enable interoperability between
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different FPGA tools) adopted by the F4PGA toolchain:
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* [FPGA Interchange schema](https://github.com/chipsalliance/fpga-interchange-schema)
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* [FPGA Interchange Python utilities](https://github.com/chipsalliance/python-fpga-interchange)
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* [FPGA Interchange Test suite](https://github.com/SymbiFlow/fpga-interchange-tests)
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* The [FPGA tool performance framework](https://github.com/chipsalliance/fpga-tool-perf) framework for benchmarking
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designs against various FPGA tools, and vice versa, over time.
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* FPGA Database visualisation tools for visual exploration of FPGA bitstream and databases:
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* [F4PGA bitstream viewer](https://github.com/SymbiFlow/f4pga-bitstream-viewer)
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* [F4PGA database visualizer](https://github.com/chipsalliance/f4pga-database-visualizer)
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* Other utilities (FPGA assembly format, documentation and other):
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* [F4PGA Assembly (FASM)](https://github.com/chipsalliance/fasm)
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* [Xilinx bitstream generation library](https://github.com/SymbiFlow/f4pga-xc-fasm)
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* [Verilog-to-routing XML utilities](https://github.com/SymbiFlow/vtr-xml-utils)
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* [SDF format utilities](https://github.com/chipsalliance/python-sdf-timing)
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* [F4PGA tools data manager](https://github.com/SymbiFlow/symbiflow-tools-data-manager)
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* [F4PGA Sphinx Theme](https://github.com/SymbiFlow/sphinx_symbiflow_theme)
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* [F4PGA Sphinx HDL diagrams](https://github.com/SymbiFlow/sphinxcontrib-hdl-diagrams)
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* [F4PGA Sphinx Verilog domain](https://github.com/SymbiFlow/sphinx-verilog-domain)
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## F4PGA Workgroup
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The F4PGA Workgroup consists of members from different backgrounds, including FPGA vendors
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([Xilinx](https://www.xilinx.com/) and [QuickLogic](https://www.quicklogic.com/)),
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industrial users
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([Google](https://www.google.com/), [Antmicro](https://antmicro.com/))
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and academia
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([University of Toronto](https://www.utoronto.ca/)),
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who collaborate to build a more open source and software-driven FPGA ecosystem (IP, tools and workflows) to drive the
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adoption of FPGAs in existing and new use cases, and eliminate barriers of entry.
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