Hardware
/
f4pga
mirror of https://github.com/chipsalliance/f4pga.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
FOSS Flow For FPGA
1,037 Commits 3 Branches 0 Tags 32 MiB
Python 94.1%
Shell 2.9%
Tcl 2.4%
XSLT 0.3%
VHDL 0.1%
Other 0.2%
Go to file
Unai Martinez-Corral e0037de59f
f4pga/flows: mv common_modules modules (#638) 		2022-09-28 23:12:16 +02:00
.github f4pga/flows/yosys: support optional value 'extra_args' 2022-09-23 09:58:25 +02:00
docs Design Flows <Flows> 2022-09-25 03:01:34 +04:00
f4pga f4pga/flows/common: update docstring 2022-09-28 22:05:44 +01:00
scripts docs/changes: add 8 (#636) 2022-09-08 13:30:31 +02:00
test ci: add job 'Format' 2022-08-19 18:33:57 +02:00
third_party Bump third_party/make-env from `0696632` to `59adb0f` 2021-04-16 05:36:52 +00:00
.gitattributes add .gitattributes and .gitcommit 2022-08-02 02:21:30 +02:00
.gitcommit add .gitattributes and .gitcommit 2022-08-02 02:21:30 +02:00
.gitignore f4pga: cleanup and style 2022-04-26 12:16:38 +02:00
.gitmodules use intersphinx instead of adding submodules 2022-02-10 04:14:26 +01:00
LICENSE docs: s/http:/https:/ 2022-04-05 13:34:02 +02:00
README.md readme: content moved to the index of the docs 2022-08-10 11:41:19 +02:00
readthedocs.yml add missing headers 2022-06-02 00:35:06 +02:00

README.md

FOSS Flows For FPGA (F4PGA) project

'Automerge' workflow status

This is the top-level repository for the F4PGA project, which is a Workgroup under the CHIPS Alliance; consisting of members from different backgrounds, including FPGA vendors, industrial users and academia (see Documentation > Community); who collaborate to build a more open source and software-driven FPGA ecosystem (IP, tools and workflows) to drive the adoption of FPGAs in existing and new use cases, and eliminate barriers of entry.