FOSS Flow For FPGA
Go to file
Paweł Czarnecki e88f714877 common modules: eos-s3: add analysis stage
Signed-off-by: Paweł Czarnecki <pczarnecki@antmicro.com>
2022-08-01 13:56:04 +02:00
.github common modules: eos-s3: add analysis stage 2022-08-01 13:56:04 +02:00
docs docs/changes: examples was updated 2022-08-01 13:01:11 +02:00
f4pga common modules: eos-s3: add analysis stage 2022-08-01 13:56:04 +02:00
test add missing headers 2022-06-02 00:35:06 +02:00
third_party Bump third_party/make-env from `0696632` to `59adb0f` 2021-04-16 05:36:52 +00:00
.gitignore f4pga: cleanup and style 2022-04-26 12:16:38 +02:00
.gitmodules use intersphinx instead of adding submodules 2022-02-10 04:14:26 +01:00
LICENSE docs: s/http:/https:/ 2022-04-05 13:34:02 +02:00
README.md readme: remove base64 logos from shields 2022-06-14 10:19:48 +02:00
f4pga-env rename: share/symbiflow -> share/f4pga 2022-07-28 12:54:59 +02:00
readthedocs.yml add missing headers 2022-06-02 00:35:06 +02:00

README.md

FOSS Flows For FPGA (F4PGA) project

'Automerge' workflow status

This is the top-level repository for the F4PGA project, which is a Workgroup under the CHIPS Alliance. The elements of the project include (but are not limited to):

F4PGA Workgroup

The F4PGA Workgroup consists of members from different backgrounds, including FPGA vendors (Xilinx and QuickLogic), industrial users (Google, Antmicro) and academia (University of Toronto), who collaborate to build a more open source and software-driven FPGA ecosystem (IP, tools and workflows) to drive the adoption of FPGAs in existing and new use cases, and eliminate barriers of entry.