FOSS Flow For FPGA
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Tomasz Michalak ebf85baba5
Merge pull request from antmicro/umarcor/lattice
f4pga/flows: support ice40
2022-09-23 10:06:35 +02:00
.github f4pga/flows/yosys: support optional value 'extra_args' 2022-09-23 09:58:25 +02:00
docs docs/changes: add 8 () 2022-09-08 13:30:31 +02:00
f4pga f4pga/flows/yosys: support optional value 'extra_args' 2022-09-23 09:58:25 +02:00
scripts docs/changes: add 8 () 2022-09-08 13:30:31 +02:00
test ci: add job 'Format' 2022-08-19 18:33:57 +02:00
third_party Bump third_party/make-env from 0696632 to 59adb0f 2021-04-16 05:36:52 +00:00
.gitattributes add .gitattributes and .gitcommit 2022-08-02 02:21:30 +02:00
.gitcommit add .gitattributes and .gitcommit 2022-08-02 02:21:30 +02:00
.gitignore f4pga: cleanup and style 2022-04-26 12:16:38 +02:00
.gitmodules use intersphinx instead of adding submodules 2022-02-10 04:14:26 +01:00
LICENSE docs: s/http:/https:/ 2022-04-05 13:34:02 +02:00
README.md readme: content moved to the index of the docs 2022-08-10 11:41:19 +02:00
readthedocs.yml add missing headers 2022-06-02 00:35:06 +02:00

FOSS Flows For FPGA (F4PGA) project

'Automerge' workflow status

This is the top-level repository for the F4PGA project, which is a Workgroup under the CHIPS Alliance; consisting of members from different backgrounds, including FPGA vendors, industrial users and academia (see Documentation > Community); who collaborate to build a more open source and software-driven FPGA ecosystem (IP, tools and workflows) to drive the adoption of FPGAs in existing and new use cases, and eliminate barriers of entry.