2019-09-09 09:17:43 -04:00
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dfii_control_sel = 0x01
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dfii_control_cke = 0x02
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dfii_control_odt = 0x04
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dfii_control_reset_n = 0x08
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dfii_command_cs = 0x01
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dfii_command_we = 0x02
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dfii_command_cas = 0x04
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dfii_command_ras = 0x08
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dfii_command_wrdata = 0x10
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dfii_command_rddata = 0x20
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ddrx_mr1 = 0x301
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init_sequence = [
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("Release reset", 0, 0, dfii_control_odt|dfii_control_reset_n, 50000),
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("Bring CKE high", 0, 0, dfii_control_cke|dfii_control_odt|dfii_control_reset_n, 10000),
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("Load Mode Register 3", 0, 3, dfii_command_ras|dfii_command_cas|dfii_command_we|dfii_command_cs, 0),
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("Load Mode Register 6", 0, 6, dfii_command_ras|dfii_command_cas|dfii_command_we|dfii_command_cs, 0),
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("Load Mode Register 5", 0, 5, dfii_command_ras|dfii_command_cas|dfii_command_we|dfii_command_cs, 0),
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("Load Mode Register 4", 0, 4, dfii_command_ras|dfii_command_cas|dfii_command_we|dfii_command_cs, 0),
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("Load Mode Register 2, CWL=9", 512, 2, dfii_command_ras|dfii_command_cas|dfii_command_we|dfii_command_cs, 0),
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("Load Mode Register 1", 769, 1, dfii_command_ras|dfii_command_cas|dfii_command_we|dfii_command_cs, 0),
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("Load Mode Register 0, CL=11, BL=8", 272, 0, dfii_command_ras|dfii_command_cas|dfii_command_we|dfii_command_cs, 200),
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("ZQ Calibration", 1024, 0, dfii_command_we|dfii_command_cs, 200),
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]
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