Hardware
/
litedram
mirror of https://github.com/enjoy-digital/litedram.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

gen: add separators

This commit is contained in:
Florent Kermarrec 2019-09-03 12:37:05 +02:00
parent a782eb5aa8
commit 00ecb871c4
1 changed files with 4 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
litedram/gen.py
View File

@ -45,6 +45,7 @@ from litedram.frontend.axi import *
from litedram.frontend.bist import LiteDRAMBISTGenerator from litedram.frontend.bist import LiteDRAMBISTGenerator
from litedram.frontend.bist import LiteDRAMBISTChecker from litedram.frontend.bist import LiteDRAMBISTChecker
# IOs/Interfaces -----------------------------------------------------------------------------------
def get_common_ios(): def get_common_ios():
return [ return [
@ -178,6 +179,7 @@ class Platform(XilinxPlatform):
def __init__(self): def __init__(self):
XilinxPlatform.__init__(self, "", io=[], toolchain="vivado") XilinxPlatform.__init__(self, "", io=[], toolchain="vivado")
# CRG ----------------------------------------------------------------------------------------------
class LiteDRAMCRG(Module): class LiteDRAMCRG(Module):
def __init__(self, platform, core_config): def __init__(self, platform, core_config):
@ -213,6 +215,7 @@ class LiteDRAMCRG(Module):
iodelay_pll.create_clkout(self.cd_iodelay, core_config["iodelay_clk_freq"]) iodelay_pll.create_clkout(self.cd_iodelay, core_config["iodelay_clk_freq"])
self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_iodelay) self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_iodelay)
# Core ---------------------------------------------------------------------------------------------
class LiteDRAMCoreControl(Module, AutoCSR): class LiteDRAMCoreControl(Module, AutoCSR):
def __init__(self): def __init__(self):
@ -370,6 +373,7 @@ class LiteDRAMCore(SoCSDRAM):
else: else:
raise ValueError("Unsupported port type: {}".format(core_config["user_ports_type"])) raise ValueError("Unsupported port type: {}".format(core_config["user_ports_type"]))
# Build --------------------------------------------------------------------------------------------
def main(): def main():
parser = argparse.ArgumentParser(description="LiteDRAM standalone core generator") parser = argparse.ArgumentParser(description="LiteDRAM standalone core generator")