Merge pull request #313 from cklarhorst/master
Add MT46H128M16 and change bankmaschine to not use A10 for col addresses.
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commit
01355ff781
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@ -34,7 +34,10 @@ class _AddressSlicer:
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def col(self, address):
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split = self.colbits - self.address_align
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return Cat(Replicate(0, self.address_align), address[:split])
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if self.colbits>10: # A10 is reserved for auto-precharge, this bit needs to be skipped for col addresses
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return Cat(Replicate(0, self.address_align), address[:10-self.address_align], 0, address[10-self.address_align:split])
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else:
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return Cat(Replicate(0, self.address_align), address[:split])
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# BankMachine --------------------------------------------------------------------------------------
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@ -590,6 +590,14 @@ class MT46H64M16(LPDDRModule):
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technology_timings = _TechnologyTimings(tREFI=64e6/8192, tWTR=(2, None), tCCD=(1, None), tRRD=None)
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speedgrade_timings = {"default": _SpeedgradeTimings(tRP=15, tRCD=15, tWR=15, tRFC=(None, 72), tFAW=None, tRAS=None)}
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class MT46H128M16(LPDDRModule):
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# geometry
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nbanks = 4
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nrows = 16384
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ncols = 2048
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# timings
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technology_timings = _TechnologyTimings(tREFI=64e6/8192, tWTR=(2, None), tCCD=(1, None), tRRD=None)
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speedgrade_timings = {"default": _SpeedgradeTimings(tRP=15, tRCD=15, tWR=15, tRFC=(None, 72), tFAW=None, tRAS=None)}
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class MT46H32M32(LPDDRModule):
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# geometry
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