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Merge pull request #313 from cklarhorst/master 

Add MT46H128M16 and change bankmaschine to not use A10 for col addresses.
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enjoy-digital 2023-07-07 08:53:25 +02:00 committed by GitHub
parent 6f53acae22 cf893a9839
commit 01355ff781
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2 changed files with 12 additions and 1 deletions
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3
litedram/core/bankmachine.py
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@ -34,6 +34,9 @@ class _AddressSlicer:
def col(self, address): def col(self, address):
split = self.colbits - self.address_align split = self.colbits - self.address_align
if self.colbits>10: # A10 is reserved for auto-precharge, this bit needs to be skipped for col addresses
return Cat(Replicate(0, self.address_align), address[:10-self.address_align], 0, address[10-self.address_align:split])
else:
return Cat(Replicate(0, self.address_align), address[:split]) return Cat(Replicate(0, self.address_align), address[:split])
# BankMachine -------------------------------------------------------------------------------------- # BankMachine --------------------------------------------------------------------------------------

8
litedram/modules.py
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@ -590,6 +590,14 @@ class MT46H64M16(LPDDRModule):
technology_timings = _TechnologyTimings(tREFI=64e6/8192, tWTR=(2, None), tCCD=(1, None), tRRD=None) technology_timings = _TechnologyTimings(tREFI=64e6/8192, tWTR=(2, None), tCCD=(1, None), tRRD=None)
speedgrade_timings = {"default": _SpeedgradeTimings(tRP=15, tRCD=15, tWR=15, tRFC=(None, 72), tFAW=None, tRAS=None)} speedgrade_timings = {"default": _SpeedgradeTimings(tRP=15, tRCD=15, tWR=15, tRFC=(None, 72), tFAW=None, tRAS=None)}
class MT46H128M16(LPDDRModule):
# geometry
nbanks = 4
nrows = 16384
ncols = 2048
# timings
technology_timings = _TechnologyTimings(tREFI=64e6/8192, tWTR=(2, None), tCCD=(1, None), tRRD=None)
speedgrade_timings = {"default": _SpeedgradeTimings(tRP=15, tRCD=15, tWR=15, tRFC=(None, 72), tFAW=None, tRAS=None)}
class MT46H32M32(LPDDRModule): class MT46H32M32(LPDDRModule):
# geometry # geometry